dds.map.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

--operation mode is arithmetic

N11L9_carry_eqn = N11L8;
N11L9 = N17_sout_node[4] $ (!N11L9_carry_eqn);

--N11L10 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~150
--operation mode is arithmetic

N11L10 = CARRY(N17_sout_node[4] & (!N11L8));


--N11L11 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~153
--operation mode is normal

N11L11_carry_eqn = N11L10;
N11L11 = N17_sout_node[5] $ (N11L11_carry_eqn);


--N32_sout_node[1] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

N32_sout_node[1]_lut_out = N32_sout_node[1] $ N32L8;
N32_sout_node[1] = DFFEAS(N32_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );

--N32L7 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~45
--operation mode is arithmetic

N32L7 = CARRY(N32_sout_node[1] & N32L8);


--N32_sout_node[2] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

N32_sout_node[2]_carry_eqn = N32L7;
N32_sout_node[2]_lut_out = N32_sout_node[2] $ (N32_sout_node[2]_carry_eqn);
N32_sout_node[2] = DFFEAS(N32_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );

--N32L10 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~49
--operation mode is arithmetic

N32L10 = CARRY(!N32L7 # !N32_sout_node[2]);


--N32_sout_node[3] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

N32_sout_node[3]_carry_eqn = N32L10;
N32_sout_node[3]_lut_out = N32_sout_node[3] $ (!N32_sout_node[3]_carry_eqn);
N32_sout_node[3] = DFFEAS(N32_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );

--N32L12 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~53
--operation mode is arithmetic

N32L12 = CARRY(N32_sout_node[3] & (!N32L10));


--N32_sout_node[4] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

N32_sout_node[4]_carry_eqn = N32L12;
N32_sout_node[4]_lut_out = N32_sout_node[4] $ (N32_sout_node[4]_carry_eqn);
N32_sout_node[4] = DFFEAS(N32_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );

--N32L14 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~57
--operation mode is arithmetic

N32L14 = CARRY(!N32L12 # !N32_sout_node[4]);


--N32_sout_node[5] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

N32_sout_node[5]_carry_eqn = N32L14;
N32_sout_node[5]_lut_out = N32_sout_node[5] $ (!N32_sout_node[5]_carry_eqn);
N32_sout_node[5] = DFFEAS(N32_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );

--N32L16 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~61
--operation mode is arithmetic

N32L16 = CARRY(N32_sout_node[5] & (!N32L14));


--N32_sout_node[6] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]
--operation mode is normal

N32_sout_node[6]_carry_eqn = N32L16;
N32_sout_node[6]_lut_out = N32_sout_node[6]_carry_eqn;
N32_sout_node[6] = DFFEAS(N32_sout_node[6]_lut_out, D1_clka, VCC, , , , , , );


--D1_cc[4] is fp:inst2|cc[4]
--operation mode is normal

D1_cc[4]_lut_out = D1L1 & (!A1L21 # !D1L3);
D1_cc[4] = DFFEAS(D1_cc[4]_lut_out, clkin, VCC, , , , , , );


--D1_cc[5] is fp:inst2|cc[5]
--operation mode is normal

D1_cc[5]_lut_out = D1L3 & (!A1L21 # !D1L1);
D1_cc[5] = DFFEAS(D1_cc[5]_lut_out, clkin, VCC, , , , , , );


--D1_cc[1] is fp:inst2|cc[1]
--operation mode is normal

D1_cc[1]_lut_out = D1L4 & (!A1L21 # !D1L3 # !D1L1);
D1_cc[1] = DFFEAS(D1_cc[1]_lut_out, clkin, VCC, , , , , , );


--D1_tout[7] is fp:inst2|tout[7]
--operation mode is normal

D1_tout[7]_lut_out = D1L12 & (!A1L20);
D1_tout[7] = DFFEAS(D1_tout[7]_lut_out, clkin, VCC, , , , , , );


--D1_tout[6] is fp:inst2|tout[6]
--operation mode is normal

D1_tout[6]_lut_out = D1L13 & (!A1L20);
D1_tout[6] = DFFEAS(D1_tout[6]_lut_out, clkin, VCC, , , , , , );


--A1L22 is rtl~83
--operation mode is normal

A1L22 = D1_tout[7] & D1_tout[6];


--D1_tout[5] is fp:inst2|tout[5]
--operation mode is normal

D1_tout[5]_lut_out = D1L15 & (!A1L20);
D1_tout[5] = DFFEAS(D1_tout[5]_lut_out, clkin, VCC, , , , , , );


--D1_tout[4] is fp:inst2|tout[4]
--operation mode is normal

D1_tout[4]_lut_out = D1L17 & (!A1L20);
D1_tout[4] = DFFEAS(D1_tout[4]_lut_out, clkin, VCC, , , , , , );


--D1_tout[3] is fp:inst2|tout[3]
--operation mode is normal

D1_tout[3]_lut_out = D1L19 & (!A1L20);
D1_tout[3] = DFFEAS(D1_tout[3]_lut_out, clkin, VCC, , , , , , );


--D1_tout[1] is fp:inst2|tout[1]
--operation mode is normal

D1_tout[1]_lut_out = D1L21 & (!A1L20);
D1_tout[1] = DFFEAS(D1_tout[1]_lut_out, clkin, VCC, , , , , , );


--D1_tout[2] is fp:inst2|tout[2]
--operation mode is normal

D1_tout[2]_lut_out = D1L23;
D1_tout[2] = DFFEAS(D1_tout[2]_lut_out, clkin, VCC, , , , , , );


--D1_tout[0] is fp:inst2|tout[0]
--operation mode is normal

D1_tout[0]_lut_out = D1L25 & (!A1L20);
D1_tout[0] = DFFEAS(D1_tout[0]_lut_out, clkin, VCC, , , , , , );


--A1L23 is rtl~84
--operation mode is normal

A1L23 = D1_tout[3] & D1_tout[1] & !D1_tout[2] & !D1_tout[0];


--A1L20 is rtl~1
--operation mode is normal

A1L20 = A1L22 & D1_tout[5] & D1_tout[4] & A1L23;


--D1_cc[0] is fp:inst2|cc[0]
--operation mode is normal

D1_cc[0]_lut_out = D1L6;
D1_cc[0] = DFFEAS(D1_cc[0]_lut_out, clkin, VCC, , , , , , );


--D1_cc[2] is fp:inst2|cc[2]
--operation mode is normal

D1_cc[2]_lut_out = D1L8;
D1_cc[2] = DFFEAS(D1_cc[2]_lut_out, clkin, VCC, , , , , , );


--D1_cc[3] is fp:inst2|cc[3]
--operation mode is normal

D1_cc[3]_lut_out = D1L10;
D1_cc[3] = DFFEAS(D1_cc[3]_lut_out, clkin, VCC, , , , , , );


--H1_q_a[7] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = D1_clka;
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[7] = H1_q_a[7]_PORT_A_data_out[0];


--H1_q_a[6] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[6]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[6]_PORT_A_address_reg = DFFE(H1_q_a[6]_PORT_A_address, H1_q_a[6]_clock_0, , , );
H1_q_a[6]_clock_0 = D1_clka;
H1_q_a[6]_PORT_A_data_out = MEMORY(, , H1_q_a[6]_PORT_A_address_reg, , , , , , H1_q_a[6]_clock_0, , , , , );
H1_q_a[6] = H1_q_a[6]_PORT_A_data_out[0];


--H1_q_a[5] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[5]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[5]_PORT_A_address_reg = DFFE(H1_q_a[5]_PORT_A_address, H1_q_a[5]_clock_0, , , );
H1_q_a[5]_clock_0 = D1_clka;
H1_q_a[5]_PORT_A_data_out = MEMORY(, , H1_q_a[5]_PORT_A_address_reg, , , , , , H1_q_a[5]_clock_0, , , , , );
H1_q_a[5] = H1_q_a[5]_PORT_A_data_out[0];


--H1_q_a[4] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[4]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[4]_PORT_A_address_reg = DFFE(H1_q_a[4]_PORT_A_address, H1_q_a[4]_clock_0, , , );
H1_q_a[4]_clock_0 = D1_clka;
H1_q_a[4]_PORT_A_data_out = MEMORY(, , H1_q_a[4]_PORT_A_address_reg, , , , , , H1_q_a[4]_clock_0, , , , , );
H1_q_a[4] = H1_q_a[4]_PORT_A_data_out[0];


--H1_q_a[3] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[3]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[3]_PORT_A_address_reg = DFFE(H1_q_a[3]_PORT_A_address, H1_q_a[3]_clock_0, , , );
H1_q_a[3]_clock_0 = D1_clka;
H1_q_a[3]_PORT_A_data_out = MEMORY(, , H1_q_a[3]_PORT_A_address_reg, , , , , , H1_q_a[3]_clock_0, , , , , );
H1_q_a[3] = H1_q_a[3]_PORT_A_data_out[0];


--H1_q_a[2] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[2]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[2]_PORT_A_address_reg = DFFE(H1_q_a[2]_PORT_A_address, H1_q_a[2]_clock_0, , , );
H1_q_a[2]_clock_0 = D1_clka;
H1_q_a[2]_PORT_A_data_out = MEMORY(, , H1_q_a[2]_PORT_A_address_reg, , , , , , H1_q_a[2]_clock_0, , , , , );
H1_q_a[2] = H1_q_a[2]_PORT_A_data_out[0];


--N17_sout_node[0] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

N17_sout_node[0]_lut_out = H1_q_a[1] $ N11L1;
N17_sout_node[0] = DFFEAS(N17_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );

--N17L3 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43
--operation mode is arithmetic

N17L3 = CARRY(H1_q_a[1] & N11L1);


--N14_sout_node[6] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]
--operation mode is normal

N14_sout_node[6]_carry_eqn = N14L13;
N14_sout_node[6]_lut_out = !N14_sout_node[6]_carry_eqn;
N14_sout_node[6] = DFFEAS(N14_sout_node[6]_lut_out, D1_clka, VCC, , , , , , );


--N17_sout_node[1] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

N17_sout_node[1]_carry_eqn = N17L3;
N17_sout_node[1]_lut_out = H1_q_a[0] $ N11L3 $ N17_sout_node[1]_carry_eqn;
N17_sout_node[1] = DFFEAS(N17_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );

--N17L5 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47
--operation mode is arithmetic

N17L5 = CARRY(H1_q_a[0] & !N11L3 & !N17L3 # !H1_q_a[0] & (!N17L3 # !N11L3));


--N17_sout_node[2] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

N17_sout_node[2]_carry_eqn = N17L5;
N17_sout_node[2]_lut_out = N11L5 $ (!N17_sout_node[2]_carry_eqn);
N17_sout_node[2] = DFFEAS(N17_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );

--N17L7 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51
--operation mode is arithmetic

N17L7 = CARRY(N11L5 & (!N17L5));