dds.map.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

--operation mode is normal

N8_sout_node[5]_lut_out = N11L11;
N8_sout_node[5] = DFFEAS(N8_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );


--N32_sout_node[0] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

N32_sout_node[0]_lut_out = !N32_sout_node[0];
N32_sout_node[0] = DFFEAS(N32_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );

--N32_cout[0] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

N32_cout[0] = CARRY(N32_sout_node[0]);


--N23_sout_node[1] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]
--operation mode is normal

N23_sout_node[1]_lut_out = N32_sout_node[1];
N23_sout_node[1] = DFFEAS(N23_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );


--N23_sout_node[2] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]
--operation mode is normal

N23_sout_node[2]_lut_out = N32_sout_node[2];
N23_sout_node[2] = DFFEAS(N23_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );


--N23_sout_node[3] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]
--operation mode is normal

N23_sout_node[3]_lut_out = N32_sout_node[3];
N23_sout_node[3] = DFFEAS(N23_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );


--N23_sout_node[4] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]
--operation mode is normal

N23_sout_node[4]_lut_out = N32_sout_node[4];
N23_sout_node[4] = DFFEAS(N23_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );


--N23_sout_node[5] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]
--operation mode is normal

N23_sout_node[5]_lut_out = N32_sout_node[5];
N23_sout_node[5] = DFFEAS(N23_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );


--N35_sout_node[0] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

N35_sout_node[0]_lut_out = N35_sout_node[0] $ N32_sout_node[6];
N35_sout_node[0] = DFFEAS(N35_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );

--N35L3 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43
--operation mode is arithmetic

N35L3 = CARRY(N35_sout_node[0] & N32_sout_node[6]);


--N35_sout_node[1] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

N35_sout_node[1]_carry_eqn = N35L3;
N35_sout_node[1]_lut_out = N35_sout_node[1] $ (N35_sout_node[1]_carry_eqn);
N35_sout_node[1] = DFFEAS(N35_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );

--N35L5 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47
--operation mode is arithmetic

N35L5 = CARRY(!N35L3 # !N35_sout_node[1]);


--N35_sout_node[2] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

N35_sout_node[2]_carry_eqn = N35L5;
N35_sout_node[2]_lut_out = N35_sout_node[2] $ (!N35_sout_node[2]_carry_eqn);
N35_sout_node[2] = DFFEAS(N35_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );

--N35L7 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51
--operation mode is arithmetic

N35L7 = CARRY(N35_sout_node[2] & (!N35L5));


--N35_sout_node[3] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

N35_sout_node[3]_carry_eqn = N35L7;
N35_sout_node[3]_lut_out = N35_sout_node[3] $ (N35_sout_node[3]_carry_eqn);
N35_sout_node[3] = DFFEAS(N35_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );

--N35L9 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55
--operation mode is arithmetic

N35L9 = CARRY(!N35L7 # !N35_sout_node[3]);


--N35_sout_node[4] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

N35_sout_node[4]_carry_eqn = N35L9;
N35_sout_node[4]_lut_out = N35_sout_node[4] $ (!N35_sout_node[4]_carry_eqn);
N35_sout_node[4] = DFFEAS(N35_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );

--N35L11 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59
--operation mode is arithmetic

N35L11 = CARRY(N35_sout_node[4] & (!N35L9));


--N35_sout_node[5] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]
--operation mode is normal

N35_sout_node[5]_carry_eqn = N35L11;
N35_sout_node[5]_lut_out = N35_sout_node[5] $ (N35_sout_node[5]_carry_eqn);
N35_sout_node[5] = DFFEAS(N35_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );


--D1L1 is fp:inst2|add~212
--operation mode is arithmetic

D1L1_carry_eqn = D1L11;
D1L1 = D1_cc[4] $ (!D1L1_carry_eqn);

--D1L2 is fp:inst2|add~214
--operation mode is arithmetic

D1L2 = CARRY(D1_cc[4] & (!D1L11));


--D1L3 is fp:inst2|add~217
--operation mode is normal

D1L3_carry_eqn = D1L2;
D1L3 = D1_cc[5] $ (D1L3_carry_eqn);


--D1L4 is fp:inst2|add~222
--operation mode is arithmetic

D1L4_carry_eqn = D1L7;
D1L4 = D1_cc[1] $ (D1L4_carry_eqn);

--D1L5 is fp:inst2|add~224
--operation mode is arithmetic

D1L5 = CARRY(!D1L7 # !D1_cc[1]);


--D1L6 is fp:inst2|add~227
--operation mode is arithmetic

D1L6 = A1L20 $ D1_cc[0];

--D1L7 is fp:inst2|add~229
--operation mode is arithmetic

D1L7 = CARRY(A1L20 & D1_cc[0]);


--D1L8 is fp:inst2|add~232
--operation mode is arithmetic

D1L8_carry_eqn = D1L5;
D1L8 = D1_cc[2] $ (!D1L8_carry_eqn);

--D1L9 is fp:inst2|add~234
--operation mode is arithmetic

D1L9 = CARRY(D1_cc[2] & (!D1L5));


--D1L10 is fp:inst2|add~237
--operation mode is arithmetic

D1L10_carry_eqn = D1L9;
D1L10 = D1_cc[3] $ (D1L10_carry_eqn);

--D1L11 is fp:inst2|add~239
--operation mode is arithmetic

D1L11 = CARRY(!D1L9 # !D1_cc[3]);


--A1L21 is rtl~82
--operation mode is normal

A1L21 = D1L4 & !D1L6 & !D1L8 & !D1L10;


--N14_sout_node[0] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

N14_sout_node[0]_lut_out = H1_q_a[7] $ N14_sout_node[0];
N14_sout_node[0] = DFFEAS(N14_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );

--N14L3 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~50
--operation mode is arithmetic

N14L3 = CARRY(H1_q_a[7] & N14_sout_node[0]);


--N14_sout_node[1] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

N14_sout_node[1]_carry_eqn = N14L3;
N14_sout_node[1]_lut_out = H1_q_a[6] $ N14_sout_node[1] $ N14_sout_node[1]_carry_eqn;
N14_sout_node[1] = DFFEAS(N14_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );

--N14L5 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~54
--operation mode is arithmetic

N14L5 = CARRY(H1_q_a[6] & !N14_sout_node[1] & !N14L3 # !H1_q_a[6] & (!N14L3 # !N14_sout_node[1]));


--N14_sout_node[2] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

N14_sout_node[2]_carry_eqn = N14L5;
N14_sout_node[2]_lut_out = H1_q_a[5] $ N14_sout_node[2] $ !N14_sout_node[2]_carry_eqn;
N14_sout_node[2] = DFFEAS(N14_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );

--N14L7 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~58
--operation mode is arithmetic

N14L7 = CARRY(H1_q_a[5] & (N14_sout_node[2] # !N14L5) # !H1_q_a[5] & N14_sout_node[2] & !N14L5);


--N14_sout_node[3] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

N14_sout_node[3]_carry_eqn = N14L7;
N14_sout_node[3]_lut_out = H1_q_a[4] $ N14_sout_node[3] $ N14_sout_node[3]_carry_eqn;
N14_sout_node[3] = DFFEAS(N14_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );

--N14L9 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~62
--operation mode is arithmetic

N14L9 = CARRY(H1_q_a[4] & !N14_sout_node[3] & !N14L7 # !H1_q_a[4] & (!N14L7 # !N14_sout_node[3]));


--N14_sout_node[4] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

N14_sout_node[4]_carry_eqn = N14L9;
N14_sout_node[4]_lut_out = H1_q_a[3] $ N14_sout_node[4] $ !N14_sout_node[4]_carry_eqn;
N14_sout_node[4] = DFFEAS(N14_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );

--N14L11 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~66
--operation mode is arithmetic

N14L11 = CARRY(H1_q_a[3] & (N14_sout_node[4] # !N14L9) # !H1_q_a[3] & N14_sout_node[4] & !N14L9);


--N14_sout_node[5] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

N14_sout_node[5]_carry_eqn = N14L11;
N14_sout_node[5]_lut_out = H1_q_a[2] $ N14_sout_node[5] $ N14_sout_node[5]_carry_eqn;
N14_sout_node[5] = DFFEAS(N14_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );

--N14L13 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~70
--operation mode is arithmetic

N14L13 = CARRY(H1_q_a[2] & !N14_sout_node[5] & !N14L11 # !H1_q_a[2] & (!N14L11 # !N14_sout_node[5]));


--N11L1 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~128
--operation mode is arithmetic

N11L1 = N17_sout_node[0] $ N14_sout_node[6];

--N11L2 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~130
--operation mode is arithmetic

N11L2 = CARRY(N17_sout_node[0] & N14_sout_node[6]);


--N11L3 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~133
--operation mode is arithmetic

N11L3_carry_eqn = N11L2;
N11L3 = N17_sout_node[1] $ (N11L3_carry_eqn);

--N11L4 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~135
--operation mode is arithmetic

N11L4 = CARRY(!N11L2 # !N17_sout_node[1]);


--N11L5 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138
--operation mode is arithmetic

N11L5_carry_eqn = N11L4;
N11L5 = N17_sout_node[2] $ (!N11L5_carry_eqn);

--N11L6 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~140
--operation mode is arithmetic

N11L6 = CARRY(N17_sout_node[2] & (!N11L4));


--N11L7 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~143
--operation mode is arithmetic

N11L7_carry_eqn = N11L6;
N11L7 = N17_sout_node[3] $ (N11L7_carry_eqn);

--N11L8 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~145
--operation mode is arithmetic

N11L8 = CARRY(!N11L6 # !N17_sout_node[3]);


--N11L9 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148