dds.map.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--G1_q_a[7] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[7]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , G1_q_a[7]_clock_enable_0);
G1_q_a[7]_clock_0 = D1_clka;
G1_q_a[7]_clock_enable_0 = clken;
G1_q_a[7]_PORT_A_data_out = MEMORY(, , G1_q_a[7]_PORT_A_address_reg, , , , , , G1_q_a[7]_clock_0, , G1_q_a[7]_clock_enable_0, , , );
G1_q_a[7]_PORT_A_data_out_reg = DFFE(G1_q_a[7]_PORT_A_data_out, G1_q_a[7]_clock_0, , , G1_q_a[7]_clock_enable_0);
G1_q_a[7] = G1_q_a[7]_PORT_A_data_out_reg[0];


--G1_q_a[6] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[6]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[6]_PORT_A_address_reg = DFFE(G1_q_a[6]_PORT_A_address, G1_q_a[6]_clock_0, , , G1_q_a[6]_clock_enable_0);
G1_q_a[6]_clock_0 = D1_clka;
G1_q_a[6]_clock_enable_0 = clken;
G1_q_a[6]_PORT_A_data_out = MEMORY(, , G1_q_a[6]_PORT_A_address_reg, , , , , , G1_q_a[6]_clock_0, , G1_q_a[6]_clock_enable_0, , , );
G1_q_a[6]_PORT_A_data_out_reg = DFFE(G1_q_a[6]_PORT_A_data_out, G1_q_a[6]_clock_0, , , G1_q_a[6]_clock_enable_0);
G1_q_a[6] = G1_q_a[6]_PORT_A_data_out_reg[0];


--G1_q_a[5] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[5]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[5]_PORT_A_address_reg = DFFE(G1_q_a[5]_PORT_A_address, G1_q_a[5]_clock_0, , , G1_q_a[5]_clock_enable_0);
G1_q_a[5]_clock_0 = D1_clka;
G1_q_a[5]_clock_enable_0 = clken;
G1_q_a[5]_PORT_A_data_out = MEMORY(, , G1_q_a[5]_PORT_A_address_reg, , , , , , G1_q_a[5]_clock_0, , G1_q_a[5]_clock_enable_0, , , );
G1_q_a[5]_PORT_A_data_out_reg = DFFE(G1_q_a[5]_PORT_A_data_out, G1_q_a[5]_clock_0, , , G1_q_a[5]_clock_enable_0);
G1_q_a[5] = G1_q_a[5]_PORT_A_data_out_reg[0];


--G1_q_a[4] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[4]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[4]_PORT_A_address_reg = DFFE(G1_q_a[4]_PORT_A_address, G1_q_a[4]_clock_0, , , G1_q_a[4]_clock_enable_0);
G1_q_a[4]_clock_0 = D1_clka;
G1_q_a[4]_clock_enable_0 = clken;
G1_q_a[4]_PORT_A_data_out = MEMORY(, , G1_q_a[4]_PORT_A_address_reg, , , , , , G1_q_a[4]_clock_0, , G1_q_a[4]_clock_enable_0, , , );
G1_q_a[4]_PORT_A_data_out_reg = DFFE(G1_q_a[4]_PORT_A_data_out, G1_q_a[4]_clock_0, , , G1_q_a[4]_clock_enable_0);
G1_q_a[4] = G1_q_a[4]_PORT_A_data_out_reg[0];


--G1_q_a[3] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[3]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[3]_PORT_A_address_reg = DFFE(G1_q_a[3]_PORT_A_address, G1_q_a[3]_clock_0, , , G1_q_a[3]_clock_enable_0);
G1_q_a[3]_clock_0 = D1_clka;
G1_q_a[3]_clock_enable_0 = clken;
G1_q_a[3]_PORT_A_data_out = MEMORY(, , G1_q_a[3]_PORT_A_address_reg, , , , , , G1_q_a[3]_clock_0, , G1_q_a[3]_clock_enable_0, , , );
G1_q_a[3]_PORT_A_data_out_reg = DFFE(G1_q_a[3]_PORT_A_data_out, G1_q_a[3]_clock_0, , , G1_q_a[3]_clock_enable_0);
G1_q_a[3] = G1_q_a[3]_PORT_A_data_out_reg[0];


--G1_q_a[2] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[2]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[2]_PORT_A_address_reg = DFFE(G1_q_a[2]_PORT_A_address, G1_q_a[2]_clock_0, , , G1_q_a[2]_clock_enable_0);
G1_q_a[2]_clock_0 = D1_clka;
G1_q_a[2]_clock_enable_0 = clken;
G1_q_a[2]_PORT_A_data_out = MEMORY(, , G1_q_a[2]_PORT_A_address_reg, , , , , , G1_q_a[2]_clock_0, , G1_q_a[2]_clock_enable_0, , , );
G1_q_a[2]_PORT_A_data_out_reg = DFFE(G1_q_a[2]_PORT_A_data_out, G1_q_a[2]_clock_0, , , G1_q_a[2]_clock_enable_0);
G1_q_a[2] = G1_q_a[2]_PORT_A_data_out_reg[0];


--G1_q_a[1] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[1]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[1]_PORT_A_address_reg = DFFE(G1_q_a[1]_PORT_A_address, G1_q_a[1]_clock_0, , , G1_q_a[1]_clock_enable_0);
G1_q_a[1]_clock_0 = D1_clka;
G1_q_a[1]_clock_enable_0 = clken;
G1_q_a[1]_PORT_A_data_out = MEMORY(, , G1_q_a[1]_PORT_A_address_reg, , , , , , G1_q_a[1]_clock_0, , G1_q_a[1]_clock_enable_0, , , );
G1_q_a[1]_PORT_A_data_out_reg = DFFE(G1_q_a[1]_PORT_A_data_out, G1_q_a[1]_clock_0, , , G1_q_a[1]_clock_enable_0);
G1_q_a[1] = G1_q_a[1]_PORT_A_data_out_reg[0];


--G1_q_a[0] is lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G1_q_a[0]_PORT_A_address = BUS(N5_sout_node[0], N5_sout_node[1], N5_sout_node[2], N5_sout_node[3], N5_sout_node[4], N5_sout_node[5], N8_sout_node[0], N8_sout_node[1], N8_sout_node[2], N8_sout_node[3], N8_sout_node[4], N8_sout_node[5]);
G1_q_a[0]_PORT_A_address_reg = DFFE(G1_q_a[0]_PORT_A_address, G1_q_a[0]_clock_0, , , G1_q_a[0]_clock_enable_0);
G1_q_a[0]_clock_0 = D1_clka;
G1_q_a[0]_clock_enable_0 = clken;
G1_q_a[0]_PORT_A_data_out = MEMORY(, , G1_q_a[0]_PORT_A_address_reg, , , , , , G1_q_a[0]_clock_0, , G1_q_a[0]_clock_enable_0, , , );
G1_q_a[0]_PORT_A_data_out_reg = DFFE(G1_q_a[0]_PORT_A_data_out, G1_q_a[0]_clock_0, , , G1_q_a[0]_clock_enable_0);
G1_q_a[0] = G1_q_a[0]_PORT_A_data_out_reg[0];


--G2_q_a[7] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[7]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[7]_PORT_A_address_reg = DFFE(G2_q_a[7]_PORT_A_address, G2_q_a[7]_clock_0, , , G2_q_a[7]_clock_enable_0);
G2_q_a[7]_clock_0 = D1_clka;
G2_q_a[7]_clock_enable_0 = clken;
G2_q_a[7]_PORT_A_data_out = MEMORY(, , G2_q_a[7]_PORT_A_address_reg, , , , , , G2_q_a[7]_clock_0, , G2_q_a[7]_clock_enable_0, , , );
G2_q_a[7]_PORT_A_data_out_reg = DFFE(G2_q_a[7]_PORT_A_data_out, G2_q_a[7]_clock_0, , , G2_q_a[7]_clock_enable_0);
G2_q_a[7] = G2_q_a[7]_PORT_A_data_out_reg[0];


--G2_q_a[6] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[6]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[6]_PORT_A_address_reg = DFFE(G2_q_a[6]_PORT_A_address, G2_q_a[6]_clock_0, , , G2_q_a[6]_clock_enable_0);
G2_q_a[6]_clock_0 = D1_clka;
G2_q_a[6]_clock_enable_0 = clken;
G2_q_a[6]_PORT_A_data_out = MEMORY(, , G2_q_a[6]_PORT_A_address_reg, , , , , , G2_q_a[6]_clock_0, , G2_q_a[6]_clock_enable_0, , , );
G2_q_a[6]_PORT_A_data_out_reg = DFFE(G2_q_a[6]_PORT_A_data_out, G2_q_a[6]_clock_0, , , G2_q_a[6]_clock_enable_0);
G2_q_a[6] = G2_q_a[6]_PORT_A_data_out_reg[0];


--G2_q_a[5] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[5]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[5]_PORT_A_address_reg = DFFE(G2_q_a[5]_PORT_A_address, G2_q_a[5]_clock_0, , , G2_q_a[5]_clock_enable_0);
G2_q_a[5]_clock_0 = D1_clka;
G2_q_a[5]_clock_enable_0 = clken;
G2_q_a[5]_PORT_A_data_out = MEMORY(, , G2_q_a[5]_PORT_A_address_reg, , , , , , G2_q_a[5]_clock_0, , G2_q_a[5]_clock_enable_0, , , );
G2_q_a[5]_PORT_A_data_out_reg = DFFE(G2_q_a[5]_PORT_A_data_out, G2_q_a[5]_clock_0, , , G2_q_a[5]_clock_enable_0);
G2_q_a[5] = G2_q_a[5]_PORT_A_data_out_reg[0];


--G2_q_a[4] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[4]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[4]_PORT_A_address_reg = DFFE(G2_q_a[4]_PORT_A_address, G2_q_a[4]_clock_0, , , G2_q_a[4]_clock_enable_0);
G2_q_a[4]_clock_0 = D1_clka;
G2_q_a[4]_clock_enable_0 = clken;
G2_q_a[4]_PORT_A_data_out = MEMORY(, , G2_q_a[4]_PORT_A_address_reg, , , , , , G2_q_a[4]_clock_0, , G2_q_a[4]_clock_enable_0, , , );
G2_q_a[4]_PORT_A_data_out_reg = DFFE(G2_q_a[4]_PORT_A_data_out, G2_q_a[4]_clock_0, , , G2_q_a[4]_clock_enable_0);
G2_q_a[4] = G2_q_a[4]_PORT_A_data_out_reg[0];


--G2_q_a[3] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[3]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[3]_PORT_A_address_reg = DFFE(G2_q_a[3]_PORT_A_address, G2_q_a[3]_clock_0, , , G2_q_a[3]_clock_enable_0);
G2_q_a[3]_clock_0 = D1_clka;
G2_q_a[3]_clock_enable_0 = clken;
G2_q_a[3]_PORT_A_data_out = MEMORY(, , G2_q_a[3]_PORT_A_address_reg, , , , , , G2_q_a[3]_clock_0, , G2_q_a[3]_clock_enable_0, , , );
G2_q_a[3]_PORT_A_data_out_reg = DFFE(G2_q_a[3]_PORT_A_data_out, G2_q_a[3]_clock_0, , , G2_q_a[3]_clock_enable_0);
G2_q_a[3] = G2_q_a[3]_PORT_A_data_out_reg[0];


--G2_q_a[2] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[2]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[2]_PORT_A_address_reg = DFFE(G2_q_a[2]_PORT_A_address, G2_q_a[2]_clock_0, , , G2_q_a[2]_clock_enable_0);
G2_q_a[2]_clock_0 = D1_clka;
G2_q_a[2]_clock_enable_0 = clken;
G2_q_a[2]_PORT_A_data_out = MEMORY(, , G2_q_a[2]_PORT_A_address_reg, , , , , , G2_q_a[2]_clock_0, , G2_q_a[2]_clock_enable_0, , , );
G2_q_a[2]_PORT_A_data_out_reg = DFFE(G2_q_a[2]_PORT_A_data_out, G2_q_a[2]_clock_0, , , G2_q_a[2]_clock_enable_0);
G2_q_a[2] = G2_q_a[2]_PORT_A_data_out_reg[0];


--G2_q_a[1] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[1]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[1]_PORT_A_address_reg = DFFE(G2_q_a[1]_PORT_A_address, G2_q_a[1]_clock_0, , , G2_q_a[1]_clock_enable_0);
G2_q_a[1]_clock_0 = D1_clka;
G2_q_a[1]_clock_enable_0 = clken;
G2_q_a[1]_PORT_A_data_out = MEMORY(, , G2_q_a[1]_PORT_A_address_reg, , , , , , G2_q_a[1]_clock_0, , G2_q_a[1]_clock_enable_0, , , );
G2_q_a[1]_PORT_A_data_out_reg = DFFE(G2_q_a[1]_PORT_A_data_out, G2_q_a[1]_clock_0, , , G2_q_a[1]_clock_enable_0);
G2_q_a[1] = G2_q_a[1]_PORT_A_data_out_reg[0];


--G2_q_a[0] is lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
G2_q_a[0]_PORT_A_address = BUS(N32L5, N23_sout_node[1], N23_sout_node[2], N23_sout_node[3], N23_sout_node[4], N23_sout_node[5], N35_sout_node[0], N35_sout_node[1], N35_sout_node[2], N35_sout_node[3], N35_sout_node[4], N35_sout_node[5]);
G2_q_a[0]_PORT_A_address_reg = DFFE(G2_q_a[0]_PORT_A_address, G2_q_a[0]_clock_0, , , G2_q_a[0]_clock_enable_0);
G2_q_a[0]_clock_0 = D1_clka;
G2_q_a[0]_clock_enable_0 = clken;
G2_q_a[0]_PORT_A_data_out = MEMORY(, , G2_q_a[0]_PORT_A_address_reg, , , , , , G2_q_a[0]_clock_0, , G2_q_a[0]_clock_enable_0, , , );
G2_q_a[0]_PORT_A_data_out_reg = DFFE(G2_q_a[0]_PORT_A_data_out, G2_q_a[0]_clock_0, , , G2_q_a[0]_clock_enable_0);
G2_q_a[0] = G2_q_a[0]_PORT_A_data_out_reg[0];


--D1_clka is fp:inst2|clka
--operation mode is normal

D1_clka_lut_out = D1_clka $ (D1L1 & D1L3 & A1L21);
D1_clka = DFFEAS(D1_clka_lut_out, clkin, VCC, , , , , , );


--N5_sout_node[0] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]
--operation mode is normal

N5_sout_node[0]_lut_out = N14_sout_node[0];
N5_sout_node[0] = DFFEAS(N5_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );


--N5_sout_node[1] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]
--operation mode is normal

N5_sout_node[1]_lut_out = N14_sout_node[1];
N5_sout_node[1] = DFFEAS(N5_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );


--N5_sout_node[2] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]
--operation mode is normal

N5_sout_node[2]_lut_out = N14_sout_node[2];
N5_sout_node[2] = DFFEAS(N5_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );


--N5_sout_node[3] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]
--operation mode is normal

N5_sout_node[3]_lut_out = N14_sout_node[3];
N5_sout_node[3] = DFFEAS(N5_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );


--N5_sout_node[4] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]
--operation mode is normal

N5_sout_node[4]_lut_out = N14_sout_node[4];
N5_sout_node[4] = DFFEAS(N5_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );


--N5_sout_node[5] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]
--operation mode is normal

N5_sout_node[5]_lut_out = N14_sout_node[5];
N5_sout_node[5] = DFFEAS(N5_sout_node[5]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[0] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
--operation mode is normal

N8_sout_node[0]_lut_out = N11L1;
N8_sout_node[0] = DFFEAS(N8_sout_node[0]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[1] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]
--operation mode is normal

N8_sout_node[1]_lut_out = N11L3;
N8_sout_node[1] = DFFEAS(N8_sout_node[1]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[2] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]
--operation mode is normal

N8_sout_node[2]_lut_out = N11L5;
N8_sout_node[2] = DFFEAS(N8_sout_node[2]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[3] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
--operation mode is normal

N8_sout_node[3]_lut_out = N11L7;
N8_sout_node[3] = DFFEAS(N8_sout_node[3]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[4] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
--operation mode is normal

N8_sout_node[4]_lut_out = N11L9;
N8_sout_node[4] = DFFEAS(N8_sout_node[4]_lut_out, D1_clka, VCC, , , , , , );


--N8_sout_node[5] is lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]