📄 dds.vwf

📁 用FPGA实现DDS,可变频,幅值由硬件完成
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 3000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clkin")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("tt")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("tt[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("tt[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "tt";
}

SIGNAL("q0")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q2")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q3")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q4")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q5")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q6")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q7")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

GROUP("q[7..0]")
{
	MEMBERS = "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7";
}

TRANSITION_LIST("clkin")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 60000;
			LEVEL 0 FOR 25.0;
			LEVEL 1 FOR 25.0;
		}
	}
}

TRANSITION_LIST("tt[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50388.189;
		LEVEL 1 FOR 2949611.811;
	}
}

TRANSITION_LIST("tt[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("tt[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("tt[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2771988.673;
		LEVEL 1 FOR 228011.327;
	}
}

TRANSITION_LIST("tt[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1394389.184;
		LEVEL 1 FOR 1377600.0;
		LEVEL 0 FOR 228010.816;
	}
}

TRANSITION_LIST("tt[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 688789.245;
		LEVEL 1 FOR 705600.0;
		LEVEL 0 FOR 672000.0;
		LEVEL 1 FOR 705600.0;
		LEVEL 0 FOR 228010.755;
	}
}

TRANSITION_LIST("tt[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 352788.757;
		LEVEL 1 FOR 336000.0;
		LEVEL 0 FOR 369600.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 336000.0;
			LEVEL 0 FOR 336000.0;
		}
		LEVEL 1 FOR 369600.0;
		LEVEL 0 FOR 228011.243;
	}
}

TRANSITION_LIST("tt[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 184788.418;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 168000.0;
			LEVEL 0 FOR 168000.0;
		}
		LEVEL 1 FOR 201600.0;
		NODE
		{
			REPEAT = 4;
			LEVEL 0 FOR 168000.0;
			LEVEL 1 FOR 168000.0;
		}
		LEVEL 0 FOR 168000.0;
		LEVEL 1 FOR 201600.0;
		LEVEL 0 FOR 168000.0;
		LEVEL 1 FOR 60011.582;
	}
}

TRANSITION_LIST("q0")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 218388.02;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 168000.0;
			LEVEL 0 FOR 168000.0;
		}
		LEVEL 1 FOR 201600.0;
		NODE
		{
			REPEAT = 4;
			LEVEL 0 FOR 168000.0;
			LEVEL 1 FOR 168000.0;
		}
		LEVEL 0 FOR 168000.0;
		LEVEL 1 FOR 201600.0;
		LEVEL 0 FOR 168000.0;
		LEVEL 1 FOR 26411.98;
	}
}

TRANSITION_LIST("q1")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 386387.462;
		LEVEL 1 FOR 336000.0;
		LEVEL 0 FOR 369600.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 336000.0;
			LEVEL 0 FOR 336000.0;
		}
		LEVEL 1 FOR 369600.0;
		LEVEL 0 FOR 194412.538;
	}
}

TRANSITION_LIST("q2")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 722388.011;
		LEVEL 1 FOR 705600.0;
		LEVEL 0 FOR 672000.0;
		LEVEL 1 FOR 705600.0;
		LEVEL 0 FOR 194411.989;
	}
}

TRANSITION_LIST("q3")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1427987.949;
		LEVEL 1 FOR 1377600.0;
		LEVEL 0 FOR 194412.051;
	}
}

TRANSITION_LIST("q4")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2805587.588;
		LEVEL 1 FOR 194412.412;
	}
}

TRANSITION_LIST("q5")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("q6")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("q7")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50387.635;
		LEVEL 1 FOR 2949612.365;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clkin";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "tt";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9;
}

DISPLAY_LINE
{
	CHANNEL = "tt[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tt[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "q[7..0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 0;
	CHILDREN = 11, 12, 13, 14, 15, 16, 17, 18;
}

DISPLAY_LINE
{
	CHANNEL = "q0";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q2";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q3";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q4";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q5";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q6";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "q7";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 10;
}

TIME_BAR
{
	TIME = 75000;
	MASTER = TRUE;
}
;
💿 文件大小 660 K
👤 上传用户 foreigngirl
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #DDS #幅值 #硬件
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