dds.fit.rpt

用FPGA实现DDS,可变频,幅值由硬件完成

; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve ASDO pin after configuration.        ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/ryu/桌面/新建文件夹/dds/dds.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 77 / 5,980 ( 1 % )       ;
;     -- Combinational with no register       ; 19                       ;
;     -- Register only                        ; 14                       ;
;     -- Combinational with a register        ; 44                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 5                        ;
;     -- 3 input functions                    ; 8                        ;
;     -- 2 input functions                    ; 44                       ;
;     -- 1 input functions                    ; 10                       ;
;     -- 0 input functions                    ; 10                       ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 38                       ;
;     -- arithmetic mode                      ; 39                       ;
;     -- qfbk mode                            ; 1                        ;
;     -- register cascade mode                ; 0                        ;
;     -- synchronous clear/load mode          ; 11                       ;
;     -- asynchronous clear/load mode         ; 0                        ;
;                                             ;                          ;
; Total LABs                                  ; 19 / 598 ( 3 % )         ;
; Logic elements in carry chains              ; 47                       ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 26 / 185 ( 14 % )        ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )           ;
; Global signals                              ; 2                        ;
; M4Ks                                        ; 17 / 20 ( 85 % )         ;
; Total memory bits                           ; 67,584 / 92,160 ( 73 % ) ;
; Total RAM block bits                        ; 78,336 / 92,160 ( 85 % ) ;
; PLLs                                        ; 0 / 2 ( 0 % )            ;
; Global clocks                               ; 2 / 8 ( 25 % )           ;
; Maximum fan-out node                        ; fp:inst2|clka            ;
; Maximum fan-out                             ; 61                       ;
; Highest non-global fan-out signal           ; clken                    ;
; Highest non-global fan-out                  ; 16                       ;
; Total fan-out                               ; 468                      ;
; Average fan-out                             ; 3.84                     ;
+---------------------------------------------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+