dds.tan.rpt

用FPGA实现DDS,可变频,幅值由硬件完成

; Worst-case tsu               ; N/A   ; None          ; 3.229 ns                         ; clken                                                                                            ; lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ram_block1a7~porta_address_reg11 ; --         ; clkin    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.947 ns                        ; lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]               ; q0                                                                                                            ; clkin      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.473 ns                        ; fr[4]                                                                                            ; bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4              ; --         ; clkin    ; 0            ;
; Clock Setup: 'clkin'         ; N/A   ; None          ; 116.39 MHz ( period = 8.592 ns ) ; bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg7 ; lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] ; clkin      ; clkin    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                  ;                                                                                                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin'                                                                                                                                                                                                                                                                                                                                                                                                                     ;