dds.map.summary

用FPGA实现DDS,可变频,幅值由硬件完成

Analysis & Synthesis Status : Successful - Mon Jul 30 13:12:34 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Total logic elements : 84
Total pins : 26
Total virtual pins : 0
Total memory bits : 67,584
Total PLLs : 0