dds.sim.rpt

用FPGA实现DDS,可变频,幅值由硬件完成

; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]     ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]              ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~69  ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~69           ; combout          ;
; |dds|clkin                                                                                                           ; |dds|clkin                                                                                                                    ; combout          ;
; |dds|q3                                                                                                              ; |dds|q3                                                                                                                       ; padio            ;
; |dds|q2                                                                                                              ; |dds|q2                                                                                                                       ; padio            ;
; |dds|q1                                                                                                              ; |dds|q1                                                                                                                       ; padio            ;
; |dds|q0                                                                                                              ; |dds|q0                                                                                                                       ; padio            ;
; |dds|tt[3]                                                                                                           ; |dds|tt[3]                                                                                                                    ; padio            ;
; |dds|tt[2]                                                                                                           ; |dds|tt[2]                                                                                                                    ; padio            ;
; |dds|tt[1]                                                                                                           ; |dds|tt[1]                                                                                                                    ; padio            ;
; |dds|tt[0]                                                                                                           ; |dds|tt[0]                                                                                                                    ; padio            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~70  ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~70           ; combout          ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                                ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                            ; Output Port Name                                                                                                              ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[6]                                      ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[5]                                      ; portadataout0    ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]            ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47         ; cout0            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 ; cout1            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]            ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51         ; cout0            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1    ; cout1            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]            ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55         ; cout             ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]            ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59         ; cout0            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59COUT1_69 ; cout1            ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]   ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]            ; regout           ;
; |dds|fp:inst2|cc[4]                                                                                                  ; |dds|fp:inst2|cc[4]                                                                                                           ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]     ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~66COUT1_80   ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]     ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~70COUT1_81   ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~133 ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]            ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~133 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~135          ; cout0            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~133 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~135COUT1_160 ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138          ; combout          ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138 ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]            ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~140          ; cout0            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~138 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~140COUT1     ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~143 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~143          ; combout          ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~143 ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]            ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~143 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~145          ; cout             ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148          ; combout          ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148 ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]            ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~150          ; cout0            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~148 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~150COUT1_161 ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~153 ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~153          ; combout          ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]~153 ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]            ; regout           ;
; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]     ; |dds|lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~61COUT1_74   ; cout1            ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[6]                                                  ; portadataout1    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[5]                                                  ; portadataout2    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[4]                                                  ; portadataout3    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[3]                                                  ; portadataout4    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[2]                                                  ; portadataout5    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1]                                                  ; portadataout6    ;
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7]                                         ; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[0]                                                  ; portadataout7    ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43         ; cout0            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]            ; regout           ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47         ; cout0            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 ; cout1            ;
; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]   ; |dds|lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]            ; regout           ;