dds.sim.rpt

用FPGA实现DDS,可变频,幅值由硬件完成

; Automatically save/load simulation netlist                      ; Off     ; Off           ;
; Disable timing delays in Timing Simulation                      ; Off     ; Off           ;
; Generate Signal Activity File                                   ; Off     ; Off           ;
; Group bus channels in simulation results                        ; Off     ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements ; On      ; On            ;
; Overwrite Waveform Inputs With Simulation Outputs               ; On      ;               ;
+-----------------------------------------------------------------+---------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------+
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+----------------------------------------------------------------------------------------------+
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+----------------------------------------------------------------------------------+
; |dds|bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      53.41 % ;
; Total nodes checked                                 ; 108          ;
; Total output ports checked                          ; 176          ;
; Total output ports with complete 1/0-value coverage ; 94           ;
; Total output ports with no 1/0-value coverage       ; 70           ;
; Total output ports with no 1-value coverage         ; 70           ;
; Total output ports with no 0-value coverage         ; 82           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                            ; Output Port Name                                                                                                              ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]                              ; |dds|lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]                                       ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[3]                                      ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[2]                                      ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[1]                                      ; portadataout0    ;
; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]                             ; |dds|lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]                                      ; portadataout0    ;
; |dds|fp:inst2|clka                                                                                                   ; |dds|fp:inst2|clka                                                                                                            ; regout           ;
; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]     ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]              ; regout           ;
; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]     ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]              ; regout           ;
; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]     ; |dds|lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]              ; regout           ;