dds.fit.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

D1_cc[4] = DFFEAS(D1_cc[4]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_cc[5] is fp:inst2|cc[5] at LC_X8_Y7_N5
--operation mode is normal

D1_cc[5]_lut_out = D1L4 & (!A1L21 # !D1L1);
D1_cc[5] = DFFEAS(D1_cc[5]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_cc[1] is fp:inst2|cc[1] at LC_X8_Y7_N4
--operation mode is normal

D1_cc[1]_lut_out = D1L5 & (!A1L21 # !D1L4 # !D1L1);
D1_cc[1] = DFFEAS(D1_cc[1]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[7] is fp:inst2|tout[7] at LC_X21_Y5_N2
--operation mode is normal

D1_tout[7]_lut_out = !A1L20 & D1L18;
D1_tout[7] = DFFEAS(D1_tout[7]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[6] is fp:inst2|tout[6] at LC_X21_Y5_N9
--operation mode is normal

D1_tout[6]_lut_out = !A1L20 & D1L19;
D1_tout[6] = DFFEAS(D1_tout[6]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--A1L22 is rtl~83 at LC_X21_Y5_N3
--operation mode is normal

A1L22 = D1_tout[6] & (D1_tout[7]);


--D1_tout[5] is fp:inst2|tout[5] at LC_X21_Y5_N6
--operation mode is normal

D1_tout[5]_lut_out = !A1L20 & (D1L22);
D1_tout[5] = DFFEAS(D1_tout[5]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[4] is fp:inst2|tout[4] at LC_X21_Y5_N5
--operation mode is normal

D1_tout[4]_lut_out = !A1L20 & D1L25;
D1_tout[4] = DFFEAS(D1_tout[4]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[3] is fp:inst2|tout[3] at LC_X21_Y5_N4
--operation mode is normal

D1_tout[3]_lut_out = !A1L20 & (D1L29);
D1_tout[3] = DFFEAS(D1_tout[3]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[1] is fp:inst2|tout[1] at LC_X21_Y5_N7
--operation mode is normal

D1_tout[1]_lut_out = !A1L20 & (D1L32);
D1_tout[1] = DFFEAS(D1_tout[1]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_tout[0] is fp:inst2|tout[0] at LC_X21_Y5_N8
--operation mode is normal

D1_tout[0]_lut_out = !A1L20 & (D1L38);
D1_tout[0] = DFFEAS(D1_tout[0]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--A1L23 is rtl~84 at LC_X20_Y5_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_tout[2]_qfbk = D1_tout[2];
A1L23 = D1_tout[1] & D1_tout[3] & !D1_tout[2]_qfbk & !D1_tout[0];

--D1_tout[2] is fp:inst2|tout[2] at LC_X20_Y5_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_tout[2] = DFFEAS(A1L23, GLOBAL(clkin), VCC, , , D1L35, , , VCC);


--A1L20 is rtl~1 at LC_X20_Y5_N7
--operation mode is normal

A1L20 = A1L22 & D1_tout[5] & D1_tout[4] & A1L23;


--D1_cc[0] is fp:inst2|cc[0] at LC_X22_Y5_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_cc[0]_lut_out = GND;
D1_cc[0] = DFFEAS(D1_cc[0]_lut_out, GLOBAL(clkin), VCC, , , D1L8, , , VCC);


--D1_cc[2] is fp:inst2|cc[2] at LC_X19_Y5_N2
--operation mode is normal

D1_cc[2]_lut_out = D1L11;
D1_cc[2] = DFFEAS(D1_cc[2]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--D1_cc[3] is fp:inst2|cc[3] at LC_X23_Y5_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_cc[3]_lut_out = GND;
D1_cc[3] = DFFEAS(D1_cc[3]_lut_out, GLOBAL(clkin), VCC, , , D1L14, , , VCC);


--H1_q_a[7] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[7] at M4K_X17_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[7] = H1_q_a[7]_PORT_A_data_out[0];

--H1_q_a[0] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[0] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[0] = H1_q_a[7]_PORT_A_data_out[7];

--H1_q_a[1] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[1] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[1] = H1_q_a[7]_PORT_A_data_out[6];

--H1_q_a[2] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[2] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[2] = H1_q_a[7]_PORT_A_data_out[5];

--H1_q_a[3] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[3] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[3] = H1_q_a[7]_PORT_A_data_out[4];

--H1_q_a[4] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[4] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[4] = H1_q_a[7]_PORT_A_data_out[3];

--H1_q_a[5] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[5] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[5] = H1_q_a[7]_PORT_A_data_out[2];

--H1_q_a[6] is bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|q_a[6] at M4K_X17_Y12
H1_q_a[7]_PORT_A_address = BUS(fr[0], fr[1], fr[2], fr[3], fr[4], fr[5], fr[6], fr[7]);
H1_q_a[7]_PORT_A_address_reg = DFFE(H1_q_a[7]_PORT_A_address, H1_q_a[7]_clock_0, , , );
H1_q_a[7]_clock_0 = GLOBAL(D1_clka);
H1_q_a[7]_PORT_A_data_out = MEMORY(, , H1_q_a[7]_PORT_A_address_reg, , , , , , H1_q_a[7]_clock_0, , , , , );
H1_q_a[6] = H1_q_a[7]_PORT_A_data_out[1];


--N17_sout_node[0] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] at LC_X14_Y7_N1
--operation mode is arithmetic

N17_sout_node[0]_lut_out = N11L1 $ H1_q_a[1];
N17_sout_node[0] = DFFEAS(N17_sout_node[0]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N17L3 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 at LC_X14_Y7_N1
--operation mode is arithmetic

N17L3_cout_0 = N11L1 & H1_q_a[1];
N17L3 = CARRY(N17L3_cout_0);

--N17L4 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 at LC_X14_Y7_N1
--operation mode is arithmetic

N17L4_cout_1 = N11L1 & H1_q_a[1];
N17L4 = CARRY(N17L4_cout_1);


--N14_sout_node[6] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] at LC_X19_Y12_N7
--operation mode is normal

N14_sout_node[6]_carry_eqn = (!N14L12 & N14L19) # (N14L12 & N14L20);
N14_sout_node[6]_lut_out = !N14_sout_node[6]_carry_eqn;
N14_sout_node[6] = DFFEAS(N14_sout_node[6]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );


--N17_sout_node[1] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1] at LC_X14_Y7_N2
--operation mode is arithmetic

N17_sout_node[1]_lut_out = N11L4 $ H1_q_a[0] $ N17L3;
N17_sout_node[1] = DFFEAS(N17_sout_node[1]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N17L6 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 at LC_X14_Y7_N2
--operation mode is arithmetic

N17L6_cout_0 = N11L4 & !H1_q_a[0] & !N17L3 # !N11L4 & (!N17L3 # !H1_q_a[0]);
N17L6 = CARRY(N17L6_cout_0);

--N17L7 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 at LC_X14_Y7_N2
--operation mode is arithmetic

N17L7_cout_1 = N11L4 & !H1_q_a[0] & !N17L4 # !N11L4 & (!N17L4 # !H1_q_a[0]);
N17L7 = CARRY(N17L7_cout_1);


--N17_sout_node[2] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2] at LC_X14_Y7_N3
--operation mode is arithmetic

N17_sout_node[2]_lut_out = N11L7 $ (!N17L6);
N17_sout_node[2] = DFFEAS(N17_sout_node[2]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N17L9 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 at LC_X14_Y7_N3
--operation mode is arithmetic

N17L9_cout_0 = N11L7 & (!N17L6);
N17L9 = CARRY(N17L9_cout_0);

--N17L10 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1 at LC_X14_Y7_N3
--operation mode is arithmetic

N17L10_cout_1 = N11L7 & (!N17L7);
N17L10 = CARRY(N17L10_cout_1);


--N17_sout_node[3] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] at LC_X14_Y7_N4
--operation mode is arithmetic

N17_sout_node[3]_lut_out = N11L10 $ N17L9;
N17_sout_node[3] = DFFEAS(N17_sout_node[3]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N17L12 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 at LC_X14_Y7_N4
--operation mode is arithmetic

N17L12 = N17L13;


--N17_sout_node[4] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] at LC_X14_Y7_N5
--operation mode is arithmetic

N17_sout_node[4]_carry_eqn = (!N17L12 & GND) # (N17L12 & VCC);
N17_sout_node[4]_lut_out = N11L14 $ !N17_sout_node[4]_carry_eqn;
N17_sout_node[4] = DFFEAS(N17_sout_node[4]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N17L16 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59 at LC_X14_Y7_N5
--operation mode is arithmetic

N17L16_cout_0 = N11L14 & !N17L12;
N17L16 = CARRY(N17L16_cout_0);

--N17L17 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59COUT1_69 at LC_X14_Y7_N5
--operation mode is arithmetic

N17L17_cout_1 = N11L14 & !N17L12;
N17L17 = CARRY(N17L17_cout_1);


--N17_sout_node[5] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] at LC_X14_Y7_N6
--operation mode is normal

N17_sout_node[5]_carry_eqn = (!N17L12 & N17L16) # (N17L12 & N17L17);
N17_sout_node[5]_lut_out = N17_sout_node[5]_carry_eqn $ N11L17;
N17_sout_node[5] = DFFEAS(N17_sout_node[5]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );


--D1L18 is fp:inst2|add~242 at LC_X21_Y4_N7
--operation mode is normal

D1L18_carry_eqn = (!D1L26 & D1L20) # (D1L26 & D1L21);
D1L18 = D1_tout[7] $ (D1L18_carry_eqn);


--D1L19 is fp:inst2|add~247 at LC_X21_Y4_N6
--operation mode is arithmetic