dds.fit.eqn

用FPGA实现DDS,可变频,幅值由硬件完成

N32_sout_node[0]_lut_out = !N32_sout_node[0];
N32_sout_node[0] = DFFEAS(N32_sout_node[0]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N32_cout[0] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[0] at LC_X16_Y6_N8
--operation mode is arithmetic

N32_cout[0]_cout_0 = N32_sout_node[0];
N32_cout[0] = CARRY(N32_cout[0]_cout_0);

--N32L3 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[0]~COUT1 at LC_X16_Y6_N8
--operation mode is arithmetic

N32L3_cout_1 = N32_sout_node[0];
N32L3 = CARRY(N32L3_cout_1);


--N23_sout_node[1] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1] at LC_X16_Y5_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

N23_sout_node[1]_lut_out = GND;
N23_sout_node[1] = DFFEAS(N23_sout_node[1]_lut_out, GLOBAL(D1_clka), VCC, , , N32_sout_node[1], , , VCC);


--N23_sout_node[2] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2] at LC_X16_Y6_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

N23_sout_node[2]_lut_out = GND;
N23_sout_node[2] = DFFEAS(N23_sout_node[2]_lut_out, GLOBAL(D1_clka), VCC, , , N32_sout_node[2], , , VCC);


--N23_sout_node[3] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3] at LC_X16_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

N23_sout_node[3]_lut_out = GND;
N23_sout_node[3] = DFFEAS(N23_sout_node[3]_lut_out, GLOBAL(D1_clka), VCC, , , N32_sout_node[3], , , VCC);


--N23_sout_node[4] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] at LC_X16_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

N23_sout_node[4]_lut_out = GND;
N23_sout_node[4] = DFFEAS(N23_sout_node[4]_lut_out, GLOBAL(D1_clka), VCC, , , N32_sout_node[4], , , VCC);


--N23_sout_node[5] is lpm_add_sub2:inst6|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5] at LC_X16_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

N23_sout_node[5]_lut_out = GND;
N23_sout_node[5] = DFFEAS(N23_sout_node[5]_lut_out, GLOBAL(D1_clka), VCC, , , N32_sout_node[5], , , VCC);


--N35_sout_node[0] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] at LC_X16_Y4_N1
--operation mode is arithmetic

N35_sout_node[0]_lut_out = N35_sout_node[0] $ N32_sout_node[6];
N35_sout_node[0] = DFFEAS(N35_sout_node[0]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N35L3 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43 at LC_X16_Y4_N1
--operation mode is arithmetic

N35L3_cout_0 = N35_sout_node[0] & N32_sout_node[6];
N35L3 = CARRY(N35L3_cout_0);

--N35L4 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~43COUT1_67 at LC_X16_Y4_N1
--operation mode is arithmetic

N35L4_cout_1 = N35_sout_node[0] & N32_sout_node[6];
N35L4 = CARRY(N35L4_cout_1);


--N35_sout_node[1] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1] at LC_X16_Y4_N2
--operation mode is arithmetic

N35_sout_node[1]_lut_out = N35_sout_node[1] $ (N35L3);
N35_sout_node[1] = DFFEAS(N35_sout_node[1]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N35L6 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47 at LC_X16_Y4_N2
--operation mode is arithmetic

N35L6_cout_0 = !N35L3 # !N35_sout_node[1];
N35L6 = CARRY(N35L6_cout_0);

--N35L7 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~47COUT1_68 at LC_X16_Y4_N2
--operation mode is arithmetic

N35L7_cout_1 = !N35L4 # !N35_sout_node[1];
N35L7 = CARRY(N35L7_cout_1);


--N35_sout_node[2] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2] at LC_X16_Y4_N3
--operation mode is arithmetic

N35_sout_node[2]_lut_out = N35_sout_node[2] $ !N35L6;
N35_sout_node[2] = DFFEAS(N35_sout_node[2]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N35L9 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51 at LC_X16_Y4_N3
--operation mode is arithmetic

N35L9_cout_0 = N35_sout_node[2] & !N35L6;
N35L9 = CARRY(N35L9_cout_0);

--N35L10 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~51COUT1 at LC_X16_Y4_N3
--operation mode is arithmetic

N35L10_cout_1 = N35_sout_node[2] & !N35L7;
N35L10 = CARRY(N35L10_cout_1);


--N35_sout_node[3] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] at LC_X16_Y4_N4
--operation mode is arithmetic

N35_sout_node[3]_lut_out = N35_sout_node[3] $ N35L9;
N35_sout_node[3] = DFFEAS(N35_sout_node[3]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N35L12 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~55 at LC_X16_Y4_N4
--operation mode is arithmetic

N35L12 = N35L13;


--N35_sout_node[4] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] at LC_X16_Y4_N5
--operation mode is arithmetic

N35_sout_node[4]_carry_eqn = (!N35L12 & GND) # (N35L12 & VCC);
N35_sout_node[4]_lut_out = N35_sout_node[4] $ !N35_sout_node[4]_carry_eqn;
N35_sout_node[4] = DFFEAS(N35_sout_node[4]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N35L16 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59 at LC_X16_Y4_N5
--operation mode is arithmetic

N35L16_cout_0 = N35_sout_node[4] & !N35L12;
N35L16 = CARRY(N35L16_cout_0);

--N35L17 is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~59COUT1_69 at LC_X16_Y4_N5
--operation mode is arithmetic

N35L17_cout_1 = N35_sout_node[4] & !N35L12;
N35L17 = CARRY(N35L17_cout_1);


--N35_sout_node[5] is lpm_add_sub2:inst5|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] at LC_X16_Y4_N6
--operation mode is normal

N35_sout_node[5]_carry_eqn = (!N35L12 & N35L16) # (N35L12 & N35L17);
N35_sout_node[5]_lut_out = N35_sout_node[5]_carry_eqn $ N35_sout_node[5];
N35_sout_node[5] = DFFEAS(N35_sout_node[5]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );


--D1L1 is fp:inst2|add~212 at LC_X20_Y5_N5
--operation mode is arithmetic

D1L1_carry_eqn = (!D1L15 & GND) # (D1L15 & VCC);
D1L1 = D1_cc[4] $ !D1L1_carry_eqn;

--D1L2 is fp:inst2|add~214 at LC_X20_Y5_N5
--operation mode is arithmetic

D1L2_cout_0 = D1_cc[4] & !D1L15;
D1L2 = CARRY(D1L2_cout_0);

--D1L3 is fp:inst2|add~214COUT1_285 at LC_X20_Y5_N5
--operation mode is arithmetic

D1L3_cout_1 = D1_cc[4] & !D1L15;
D1L3 = CARRY(D1L3_cout_1);


--D1L4 is fp:inst2|add~217 at LC_X20_Y5_N6
--operation mode is normal

D1L4_carry_eqn = (!D1L15 & D1L2) # (D1L15 & D1L3);
D1L4 = D1L4_carry_eqn $ D1_cc[5];


--D1L5 is fp:inst2|add~222 at LC_X20_Y5_N2
--operation mode is arithmetic

D1L5 = D1_cc[1] $ (D1L9);

--D1L6 is fp:inst2|add~224 at LC_X20_Y5_N2
--operation mode is arithmetic

D1L6_cout_0 = !D1L9 # !D1_cc[1];
D1L6 = CARRY(D1L6_cout_0);

--D1L7 is fp:inst2|add~224COUT1_284 at LC_X20_Y5_N2
--operation mode is arithmetic

D1L7_cout_1 = !D1L10 # !D1_cc[1];
D1L7 = CARRY(D1L7_cout_1);


--D1L8 is fp:inst2|add~227 at LC_X20_Y5_N1
--operation mode is arithmetic

D1L8 = A1L20 $ D1_cc[0];

--D1L9 is fp:inst2|add~229 at LC_X20_Y5_N1
--operation mode is arithmetic

D1L9_cout_0 = A1L20 & D1_cc[0];
D1L9 = CARRY(D1L9_cout_0);

--D1L10 is fp:inst2|add~229COUT1_283 at LC_X20_Y5_N1
--operation mode is arithmetic

D1L10_cout_1 = A1L20 & D1_cc[0];
D1L10 = CARRY(D1L10_cout_1);


--D1L11 is fp:inst2|add~232 at LC_X20_Y5_N3
--operation mode is arithmetic

D1L11 = D1_cc[2] $ !D1L6;

--D1L12 is fp:inst2|add~234 at LC_X20_Y5_N3
--operation mode is arithmetic

D1L12_cout_0 = D1_cc[2] & !D1L6;
D1L12 = CARRY(D1L12_cout_0);

--D1L13 is fp:inst2|add~234COUT1 at LC_X20_Y5_N3
--operation mode is arithmetic

D1L13_cout_1 = D1_cc[2] & !D1L7;
D1L13 = CARRY(D1L13_cout_1);


--D1L14 is fp:inst2|add~237 at LC_X20_Y5_N4
--operation mode is arithmetic

D1L14 = D1_cc[3] $ (D1L12);

--D1L15 is fp:inst2|add~239 at LC_X20_Y5_N4
--operation mode is arithmetic

D1L15 = D1L16;


--A1L21 is rtl~82 at LC_X20_Y5_N9
--operation mode is normal

A1L21 = D1L5 & !D1L11 & !D1L14 & !D1L8;


--N14_sout_node[0] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0] at LC_X19_Y12_N1
--operation mode is arithmetic

N14_sout_node[0]_lut_out = N14_sout_node[0] $ H1_q_a[7];
N14_sout_node[0] = DFFEAS(N14_sout_node[0]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N14L3 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~50 at LC_X19_Y12_N1
--operation mode is arithmetic

N14L3_cout_0 = N14_sout_node[0] & H1_q_a[7];
N14L3 = CARRY(N14L3_cout_0);

--N14L4 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[0]~50COUT1_78 at LC_X19_Y12_N1
--operation mode is arithmetic

N14L4_cout_1 = N14_sout_node[0] & H1_q_a[7];
N14L4 = CARRY(N14L4_cout_1);


--N14_sout_node[1] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1] at LC_X19_Y12_N2
--operation mode is arithmetic

N14_sout_node[1]_lut_out = N14_sout_node[1] $ H1_q_a[6] $ N14L3;
N14_sout_node[1] = DFFEAS(N14_sout_node[1]_lut_out, GLOBAL(D1_clka), VCC, , , , , , );

--N14L6 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~54 at LC_X19_Y12_N2
--operation mode is arithmetic

N14L6_cout_0 = N14_sout_node[1] & !H1_q_a[6] & !N14L3 # !N14_sout_node[1] & (!N14L3 # !H1_q_a[6]);
N14L6 = CARRY(N14L6_cout_0);

--N14L7 is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]~54COUT1_79 at LC_X19_Y12_N2
--operation mode is arithmetic

N14L7_cout_1 = N14_sout_node[1] & !H1_q_a[6] & !N14L4 # !N14_sout_node[1] & (!N14L4 # !H1_q_a[6]);
N14L7 = CARRY(N14L7_cout_1);


--N14_sout_node[2] is lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2] at LC_X19_Y12_N3
--operation mode is arithmetic