dds.tan.summary

用FPGA实现DDS,可变频,幅值由硬件完成

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.229 ns
From           : clken
To             : lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ram_block1a7~porta_address_reg11
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.947 ns
From           : lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|q_a[0]
To             : q0
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.473 ns
From           : fr[4]
To             : bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg4
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : N/A
Required Time  : None
Actual Time    : 116.39 MHz ( period = 8.592 ns )
From           : bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ram_block1a7~porta_address_reg7
To             : lpm_add_sub2:inst3|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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