dds.fit.summary

用FPGA实现DDS,可变频,幅值由硬件完成

Fitter Status : Successful - Mon Jul 30 13:12:42 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 77 / 5,980 ( 1 % )
Total pins : 26 / 185 ( 14 % )
Total virtual pins : 0
Total memory bits : 67,584 / 92,160 ( 73 % )
Total PLLs : 0 / 2 ( 0 % )