dds.map.rpt
来自「用FPGA实现DDS,可变频,幅值由硬件完成」· RPT 代码 · 共 601 行 · 第 1/5 页
RPT
601 行
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------------------------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------------------------------------------------+
; bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 8 ; -- ; -- ; 2048 ; dds0.rtl.mif ;
; lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 4096 ; 8 ; -- ; -- ; 32768 ; C:/Documents and Settings/ryu/桌面/新建文件夹/Mif1.mif ;
; lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 4096 ; 8 ; -- ; -- ; 32768 ; C:/Documents and Settings/ryu/桌面/新建文件夹/Mif1.mif ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 58 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom1:inst|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom1:inst9|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+---------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------------------+
+-----------------------------------------------------------------------------------------+
; Source assignments for bianma1:inst1|altsyncram:Mux_rtl_0|altsyncram_btk:auto_generated ;
+---------------------------------+--------------------+------+---------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+---------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom1:inst|altsyncram:altsyncram_component ;
+------------------------------------+--------------------------------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------------------------+----------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 12 ; Integer ;
; NUMWORDS_A ; 4096 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; C:/Documents and Settings/ryu/桌面/新建文件夹/Mif1.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_dpu ; Untyped ;
+------------------------------------+--------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_add_sub2:inst4|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------------------------+
; LPM_WIDTH ; 12 ; Integer ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 1 ; Integer ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
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