rrr.vhd

来自「用FPGA实现DDS,可变频,幅值由硬件完成」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rrr is
port(
	clk:in std_logic;
	en:in std_logic;
	address:out integer range 0 to 4095
);
end rrr;

architecture aaaa of rrr is
begin
process(clk)
variable ss:integer range 0 to 4095;
begin
if clk'event and clk='1' then
	if en='1' then
		if ss=4095 then
			ss:=0;
		else
			ss:=ss+1;
		end if;
	elsif en='0' then ss:=0;
	end if;
end if;
address<=ss;
end process;
end aaaa;