shijizhi.fit.qmsg

十进制加法计数器.VHDL程序,可在Quratus 2中运行

{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "5 unused 3.30 0 5 0 " "Info: Number of I/O pins in group: 5 (unused VREF, 3.30 VCCIO, 0 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 8 13 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  13 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.871 ns register register " "Info: Estimated most critical path is register to register delay of 1.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[1\] 1 REG LAB_X2_Y13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'b\[1\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "" { b[1] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.065 ns) + CELL(0.590 ns) 0.655 ns add~8 2 COMB LAB_X2_Y13 1 " "Info: 2: + IC(0.065 ns) + CELL(0.590 ns) = 0.655 ns; Loc. = LAB_X2_Y13; Fanout = 1; COMB Node = 'add~8'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "0.655 ns" { b[1] add~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.867 ns) 1.871 ns b\[2\] 3 REG LAB_X2_Y13 5 " "Info: 3: + IC(0.349 ns) + CELL(0.867 ns) = 1.871 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'b\[2\]'" {  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.216 ns" { add~8 b[2] } "NODE_NAME" } } } { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" "" "" { Text "d:/quartus ii/qdesigns41sp2/liu/shijizhi/shijizhi.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 77.87 % " "Info: Total cell delay = 1.457 ns ( 77.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.414 ns 22.13 % " "Info: Total interconnect delay = 0.414 ns ( 22.13 % )" {  } {  } 0}  } { { "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" "" "" { Report "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi_cmp.qrpt" Compiler "shijizhi" "UNKNOWN" "V1" "d:/quartus ii/qdesigns41sp2/liu/shijizhi/db/shijizhi.quartus_db" { Floorplan "" "" "1.871 ns" { b[1] add~8 b[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 04 11:04:27 2007 " "Info: Processing ended: Sat Aug 04 11:04:27 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}