_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity rs_test is
    generic(
        testencpause    : integer := 0;
        testpause       : integer := 0;
        testvariablek   : integer := 1;
        testvariablet   : integer := 1;
        swidth          : integer := 8;
        twidth          : integer := 4;
        period          : integer := 20;
        asyncrststart   : integer := 107;
        asyncrst        : integer := 36;
        start           : integer := 10;
        st0             : integer := 0;
        st_start        : integer := 1;
        st_enc          : integer := 2;
        st_waitdec      : integer := 8;
        st_decdata      : integer := 9
    );
end rs_test;