_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 48 行

library verilog;
use verilog.vl_types.all;
entity syndrome is
    generic(
        swidth          : integer := 8;
        twidth          : integer := 4;
        maxt            : integer := 8;
        beta0           : integer := 1;
        beta1           : integer := 2;
        beta2           : integer := 4;
        beta3           : integer := 8;
        beta4           : integer := 16;
        beta5           : integer := 32;
        beta6           : integer := 64;
        beta7           : integer := 128;
        beta8           : integer := 29;
        beta9           : integer := 58;
        beta10          : integer := 116;
        beta11          : integer := 232;
        beta12          : integer := 205;
        beta13          : integer := 135;
        beta14          : integer := 19;
        beta15          : integer := 38
    );
    port(
        async_reset     : in     vl_logic;
        clk             : in     vl_logic;
        enable_i        : in     vl_logic;
        syndromestart_i : in     vl_logic;
        loadcode_i      : in     vl_logic;
        code_i          : in     vl_logic_vector;
        k_i             : in     vl_logic_vector;
        t_i             : in     vl_logic_vector;
        sindexb_i       : in     vl_logic_vector;
        sindexc_i       : in     vl_logic_vector;
        fifonotfull_i   : in     vl_logic;
        switchsc_i      : in     vl_logic;
        data_o          : out    vl_logic_vector;
        write_o         : out    vl_logic;
        validword_o     : out    vl_logic;
        k_o             : out    vl_logic_vector;
        t_o             : out    vl_logic_vector;
        sb_o            : out    vl_logic_vector;
        sc_o            : out    vl_logic_vector;
        startberlekamp_o: out    vl_logic
    );
end syndrome;