_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 43 行

library verilog;
use verilog.vl_types.all;
entity forney is
    generic(
        maxt            : integer := 8;
        twidth          : integer := 4;
        swidth          : integer := 8;
        st_0            : integer := 0;
        st_omegainvx1   : integer := 1;
        st_doy          : integer := 2;
        st_final        : integer := 3
    );
    port(
        async_reset     : in     vl_logic;
        clk             : in     vl_logic;
        enable_i        : in     vl_logic;
        forneystart_i   : in     vl_logic;
        validword_i     : in     vl_logic;
        success_i       : in     vl_logic;
        k_i             : in     vl_logic_vector;
        t_i             : in     vl_logic_vector;
        v_i             : in     vl_logic_vector;
        omega_i         : in     vl_logic_vector;
        x_i             : in     vl_logic_vector;
        invx_i          : in     vl_logic_vector;
        inverse_i       : in     vl_logic_vector;
        yindex_i        : in     vl_logic_vector;
        forneydone_o    : out    vl_logic;
        validword_o     : out    vl_logic;
        success_o       : out    vl_logic;
        k_o             : out    vl_logic_vector;
        v_o             : out    vl_logic_vector;
        y_o             : out    vl_logic_vector;
        invdata_o       : out    vl_logic_vector;
        finvactive_o    : out    vl_logic;
        omegaindex_o    : out    vl_logic_vector;
        xindex_o        : out    vl_logic_vector;
        invxindex_o     : out    vl_logic_vector;
        startoutput_o   : out    vl_logic;
        switchpos_o     : out    vl_logic
    );
end forney;