_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity rs_dec is
    generic(
        twidth          : integer := 4;
        swidth          : integer := 8
    );
    port(
        async_reset     : in     vl_logic;
        clk             : in     vl_logic;
        clk_en          : in     vl_logic;
        datain          : in     vl_logic_vector;
        load            : in     vl_logic;
        k               : in     vl_logic_vector;
        t               : in     vl_logic_vector;
        firstsymbol_i   : in     vl_logic;
        dataout         : out    vl_logic_vector;
        store           : out    vl_logic;
        success         : out    vl_logic;
        error_count     : out    vl_logic_vector;
        firstdata_o     : out    vl_logic
    );
end rs_dec;