_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity dualportram is
    generic(
        datawidth       : integer := 12;
        addrwidth       : integer := 9;
        size            : integer := 512
    );
    port(
        clk_i           : in     vl_logic;
        ra_i            : in     vl_logic_vector;
        wa_i            : in     vl_logic_vector;
        we_i            : in     vl_logic;
        d_i             : in     vl_logic_vector;
        q_o             : out    vl_logic_vector
    );
end dualportram;