_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity innerchien is
    generic(
        swidth          : integer := 8;
        betafirst       : integer := 100;
        lbetafirst      : integer := 100;
        lbetalast       : integer := 100;
        maxt            : integer := 8;
        twidth          : integer := 4;
        invalpha        : integer := 142;
        st0             : integer := 0;
        st_eval         : integer := 1;
        st_next         : integer := 2;
        st_end          : integer := 3
    );
    port(
        async_reset     : in     vl_logic;
        clk             : in     vl_logic;
        enable_i        : in     vl_logic;
        innerchienstart_i: in     vl_logic;
        switchregs_i    : in     vl_logic;
        validword_i     : in     vl_logic;
        eval_i          : in     vl_logic;
        e_i             : in     vl_logic_vector;
        innerposindex_i : in     vl_logic_vector;
        k_i             : in     vl_logic_vector;
        t_i             : in     vl_logic_vector;
        innerchiendone_o: out    vl_logic;
        innerpos_o      : out    vl_logic_vector;
        jc_o            : out    vl_logic_vector
    );
end innerchien;