_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity rs_enc is
    generic(
        swidth          : integer := 8;
        twidth          : integer := 4;
        maxt            : integer := 8
    );
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        enable_i        : in     vl_logic;
        loaddata_i      : in     vl_logic;
        start_i         : in     vl_logic;
        paramk_i        : in     vl_logic_vector;
        paramt_i        : in     vl_logic_vector;
        data_i          : in     vl_logic_vector;
        firstsymbol_o   : out    vl_logic;
        code_o          : out    vl_logic_vector;
        storecode_o     : out    vl_logic;
        parity_o        : out    vl_logic
    );
end rs_enc;