_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity invrom is
    generic(
        swidth          : integer := 8
    );
    port(
        addrb_i         : in     vl_logic_vector;
        addrf_i         : in     vl_logic_vector;
        binvactive_i    : in     vl_logic;
        finvactive_i    : in     vl_logic;
        data_o          : out    vl_logic_vector;
        binvdelay_o     : out    vl_logic
    );
end invrom;