_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity outputmodule is
    generic(
        swidth          : integer := 8;
        twidth          : integer := 4;
        st_0            : integer := 0;
        st_wait1        : integer := 1;
        st_wait2        : integer := 2;
        st_output       : integer := 3;
        st_final        : integer := 4
    );
    port(
        async_reset_i   : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        k_i             : in     vl_logic_vector;
        v_i             : in     vl_logic_vector;
        pos_i           : in     vl_logic_vector;
        y_i             : in     vl_logic_vector;
        ramdata_i       : in     vl_logic_vector;
        dataavail_i     : in     vl_logic;
        decdone_i       : in     vl_logic;
        validword_i     : in     vl_logic;
        success_i       : in     vl_logic;
        bypass_i        : in     vl_logic;
        posindex_o      : out    vl_logic_vector;
        yindex_o        : out    vl_logic_vector;
        data_o          : out    vl_logic_vector;
        read_o          : out    vl_logic;
        validdata_o     : out    vl_logic;
        outputdone_o    : out    vl_logic;
        success_o       : out    vl_logic;
        errorcount_o    : out    vl_logic_vector;
        firstdata_o     : out    vl_logic
    );
end outputmodule;