_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity berlekamp is
    generic(
        maxt            : integer := 8;
        twidth          : integer := 4;
        swidth          : integer := 8;
        st0             : integer := 0;
        st_init         : integer := 4;
        st_evaldelta    : integer := 5;
        st_testdelta    : integer := 6;
        st_conpoly      : integer := 7;
        st_invdelta     : integer := 8;
        st_lengthensr   : integer := 9;
        st_updatelen    : integer := 10;
        st_counterrs    : integer := 11;
        st_srok         : integer := 12;
        st_tapsok       : integer := 13;
        st_test         : integer := 14;
        st_done         : integer := 15
    );
    port(
        async_reset     : in     vl_logic;
        clk             : in     vl_logic;
        enable_i        : in     vl_logic;
        berlekampstart_i: in     vl_logic;
        validword_i     : in     vl_logic;
        k_i             : in     vl_logic_vector;
        t_i             : in     vl_logic_vector;
        s_i             : in     vl_logic_vector;
        inverse_i       : in     vl_logic_vector;
        binvdelay_i     : in     vl_logic;
        eindex_i        : in     vl_logic_vector;
        eeindex_i       : in     vl_logic_vector;
        berlekampdone_o : out    vl_logic;
        validword_o     : out    vl_logic;
        success_o       : out    vl_logic;
        k_o             : out    vl_logic_vector;
        t_o             : out    vl_logic_vector;
        e_o             : out    vl_logic_vector;
        ee_o            : out    vl_logic_vector;
        v_o             : out    vl_logic_vector;
        invdata_o       : out    vl_logic_vector;
        binvactive_o    : out    vl_logic;
        sindex_o        : out    vl_logic_vector;
        startchien_o    : out    vl_logic;
        switchsc_o      : out    vl_logic
    );
end berlekamp;