_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity decode is
    generic(
        st_0            : integer := 0;
        st_1            : integer := 1;
        st_2            : integer := 2;
        tbst_0          : integer := 0;
        tbst_1          : integer := 1;
        tbst_2          : integer := 2;
        tbst_3          : integer := 3;
        tbst_4          : integer := 4;
        tbst_5          : integer := 5;
        tbst_6          : integer := 6;
        tbst_7          : integer := 7;
        tbst_8          : integer := 8;
        tbst_9          : integer := 9;
        tbst_10         : integer := 10;
        pst_0           : integer := 0;
        pst_1           : integer := 1
    );
    port(
        rst_i           : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        indec_i         : in     vl_logic_vector(7 downto 0);
        validin_i       : in     vl_logic;
        startber_i      : in     vl_logic;
        data_o          : out    vl_logic_vector(7 downto 0);
        validout_o      : out    vl_logic;
        error_o         : out    vl_logic;
        ber_o           : out    vl_logic_vector(5 downto 0);
        bervalid_o      : out    vl_logic;
        outofsync_o     : out    vl_logic
    );
end decode;