_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity fifo is
    generic(
        width           : integer := 2;
        addrwidth       : integer := 7
    );
    port(
        rst_i           : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        read_i          : in     vl_logic;
        write_i         : in     vl_logic;
        datain_i        : in     vl_logic_vector;
        notempty_o      : out    vl_logic;
        notfull_o       : out    vl_logic;
        dataout_o       : out    vl_logic_vector;
        maxfill_o       : out    vl_logic_vector
    );
end fifo;