_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity brm is
    generic(
        tab             : integer := 0
    );
    port(
        rst_i           : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        a_i             : in     vl_logic;
        indec_i         : in     vl_logic_vector(1 downto 0);
        brm_o           : out    vl_logic_vector(1 downto 0)
    );
end brm;