_primary.vhd

this come from alter ,you can look and find it on line about h263.

library verilog;
use verilog.vl_types.all;
entity acscell is
    port(
        rst_i           : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        opath1_i        : in     vl_logic_vector(5 downto 0);
        opath2_i        : in     vl_logic_vector(5 downto 0);
        brm_i           : in     vl_logic_vector(1 downto 0);
        npath1_o        : out    vl_logic_vector(5 downto 0);
        npath2_o        : out    vl_logic_vector(5 downto 0);
        brdec1_o        : out    vl_logic;
        brdec2_o        : out    vl_logic
    );
end acscell;