_primary.vhd

来自「this come from alter ,you can look and f」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity encode is
    generic(
        inwidth         : integer := 8;
        outwidth        : integer := 8;
        jwidth          : integer := 3;
        st_0            : integer := 0;
        st_1            : integer := 1
    );
    port(
        rst_i           : in     vl_logic;
        clk_i           : in     vl_logic;
        ena_i           : in     vl_logic;
        valid_i         : in     vl_logic;
        ready_i         : in     vl_logic;
        x_i             : in     vl_logic_vector;
        valid_o         : out    vl_logic;
        ready_o         : out    vl_logic;
        y_o             : out    vl_logic_vector
    );
end encode;