tb_quad.vhd

this come from alter ,you can look and find it on line.

-- TBTOP.vhd
-- -----------------------------------------------------
--   Test Bench for Quadrature Encoder
-- -----------------------------------------------------
-- (c) ALSE - Bert Cuzeau
-- [e-mail]
--
library ieee;
  use ieee.std_logic_1164.all;

entity TB_QUAD is
end;

-- ------------------------------------------------------
   architecture TEST of TB_QUAD is
-- ------------------------------------------------------

  signal Rst    : std_logic := '1';
  signal Clk    : std_logic := '0';
  signal A, B   : std_logic := '0';
  signal Cnt    : std_logic_vector(7 downto 0);
  signal Dir    : std_logic := '0';
  signal Done   : boolean;

  constant period : time := 100 ns;

begin

UUT : entity work.Quad port map
     ( Clk=>Clk, Rst=>Rst, A=>A, B=>B,
       Dir => Dir, Cnt=>Cnt  );

Clk <= '0' when Done else not Clk after (period / 2);
Rst <= '1', '0' after period;

process
begin

    wait for (5 * period);

    for i in 1 to 5 loop
      A <= '1'; wait for (8 * period);
      B <= '1'; wait for (8 * period);
      A <= '0'; wait for (8 * period);
      B <= '0'; wait for (8 * period);
    end loop;

    wait for (16 * period);

    for i in 1 to 10 loop
      B <= '1'; wait for (8 * period);
      A <= '1'; wait for (8 * period);
      B <= '0'; wait for (8 * period);
      A <= '0'; wait for (8 * period);
    end loop;

    wait for (16 * period);
    for i in 1 to 5 loop
      A <= '1'; wait for (8 * period);
      B <= '1'; wait for (8 * period);
      A <= '0'; wait for (8 * period);
      B <= '0'; wait for (8 * period);
    end loop;
  Done <= true;
  wait;
end process;

end TEST;