quad.vhd

this come from alter ,you can look and find it on line.

-- QUAD.vhd
-- --------------------------------------------
--  Quadrature Decoder State Machine
-- --------------------------------------------
-- (c) 2004 - B. Cuzeau, ALSE
-- http://www.alse-fr.com
-- Contact : [e-mail]
-- Notes :
-- * A and B must absolutely be resynchronized outside !
-- * FSM State encoding should be sequential/binary or custom (like here)
-- * Implemented as re-synchronized, one-process, Mealy State machine.
-- * Change the counter size directly in the port declaration.
-- * Cnt (n downto 2) returns the position in full turns.

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;

-- --------------------------------------------
    Entity QUAD is
-- --------------------------------------------
  port( A,B : in  std_logic; -- must absolutely be resynchronized outside
        Rst : in  std_logic;
        Clk : in  std_logic;
        Cnt : out std_logic_vector(7 downto 0); -- unsigned value !
        Dir : out std_logic );
end entity QUAD;


-- --------------------------------------------
    Architecture MealyR of QUAD is
-- --------------------------------------------

subtype SLV2 is std_logic_vector (1 downto 0);
attribute enum_encoding : string;

type   state_t is (Boot, S00, S01, S10, S11);
attribute enum_encoding of state_t : type is "100 000 001 010 011";
signal state : state_t;

signal Count : unsigned (Cnt'range);

begin

Cnt <= std_logic_vector(Count);

process (Rst,Clk)
begin
  if Rst='1' then
    State <= Boot;
    Count <= (others=>'0');
    Dir   <= '0';

  elsif rising_edge(Clk) then

    case State is

      when Boot =>
        case SLV2'(A & B) is
            when "00" => State <= S00;
            when "10" => State <= S10;
            when "11" => State <= S11;
            when "01" => State <= S01;
            when others => null;
          end case;

      when S00 =>
        case SLV2'(A & B) is
          when "10" => State <= S10;
                       Count <= Count+1;
                       Dir   <= '1';
          when "11" => null; -- possible : State <= S11;
          when "01" => State <= S01;
                       Count <= Count-1;
                       Dir   <= '0';
          when others => null;
        end case;

      when S10 =>
        case SLV2'(A & B) is
          when "00" => State <= S00;
                       Count <= Count-1;
                       Dir   <= '0';
          when "11" => State <= S11;
                       Count <= Count+1;
                       Dir   <= '1';
          when "01" => null; -- possible : State <= S01;
          when others => null;
        end case;

      when S11 =>
        case SLV2'(A & B) is
          when "10" => State <= S10;
                       Count <= Count-1;
                       Dir   <= '0';
          when "01" => State <= S01;
                       Count <= Count+1;
                       Dir   <='1';
          when "00" => null; -- possible : State <= S00;
          when others => null;
        end case;

      when S01 =>
        case SLV2'(A & B) is
          when "11" => State <= S11;
                       Count <= Count-1;
                       Dir   <= '0';
          when "00" => State <= S00;
                       Count <= Count+1;
                       Dir   <= '1';
          when "10" => null; -- possible : State <= S10;
          when others => null;
        end case;

      when others => State <= Boot;

    end case;
  end if;
end process;

end MealyR;