tb_pwm.vhd

来自「done pwm control using vhdl ,you can loo」· VHDL 代码 · 共 59 行

-- TB_PWM.vhd   (c) ALSE
-- -------------------------------------------------
--  VHDL test bench for both PWM :
--  Accumulator-based and Comparator-based Versions
-- -------------------------------------------------
-- Author  : Bertrand Cuzeau
-- Date    : July 2004
-- Version : 1.2
--
-- See the "Motor Control" Application Note on our Web site :
-- http://www.alse-fr.com


LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

entity TB_PWM is
end;

Architecture TEST of TB_PWM is

  constant Period : time := 100 ns; -- 10 MHz clock
  signal      Clk : std_logic := '0';
  signal      Rst : std_logic := '1';
  signal PWM_accum: std_logic;
  signal PWM_comp : std_logic;
  signal      Din : std_logic_vector (8 downto 0) := (others=>'0');
  signal     Done : boolean;

begin

UUT1 : Entity work.PWM (RTL_Accum)
       Port Map ( Clk=>Clk, Din=>Din, PWMout=>PWM_accum, Rst=>Rst );

UUT2 : Entity work.PWM (RTL_Comp)
       Port Map ( Clk=>Clk, Din=>Din, PWMout=>PWM_comp, Rst=>Rst );

Rst <= '0' after Period;

Clk <= '0' when Done else not Clk after Period / 2;

TB: process
begin
  for i in 0 to 31 loop
    wait until falling_edge(Clk);
    Din <= std_logic_vector (to_unsigned(I*8,9));
    wait for 256 * Period;
  end loop;
  Din <= std_logic_vector (to_unsigned(256,9));
  wait for 300 * Period;
  Done <= true;
  report "End of simulation";
  wait; -- will wait forever
end process;

end TEST;