pwm.vhd

done pwm control using vhdl ,you can look at it.

-- -----------------------------------------
--   Simple PWM ! (and One-Bit DAC)
-- -----------------------------------------
-- (c) ALSE.
-- http://www.alse-fr.com
-- Bertrand Cuzeau
--
-- Three architectures for this PWM

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;

-- -----------------------------------------
    Entity PWM is
-- -----------------------------------------
    Port (    Rst : In  std_logic;
              Clk : In  std_logic;
              Din : In  std_logic_vector (8 downto 0);
           PWMout : Out std_logic );
end PWM;


-- -----------------------------------------
    Architecture RTL_Accum of PWM is
-- -----------------------------------------
-- AKA "One-Bit DAC", "1st order delta-sima", "Pulse distribution PWM"...
-- Usually not very suitable for motor control.
-- Very useful for audio signals synthesis for example,
-- by driving a simple RC filter...

signal Accum : unsigned (8 downto 0);

begin

U1: process (Clk,Rst)
begin
  if Rst='1' then
    Accum <= (others=>'0');
  elsif rising_edge(Clk) then
    Accum <= '0' & Accum(7 downto 0) + unsigned('0' & Din(7 downto 0));
  end if;
end process U1;

U2: PWMout <= Accum(8) or Din(8);

end RTL_Accum;


-- -----------------------------------------
    Architecture RTL_Comparator of PWM is
-- -----------------------------------------
-- Simple PWM, counter + comparator solution.
-- Minimal the number of switchings.
-- Do NOT use this without registering PWM_out !!!
-- (see RTL_comp below)

signal Cnt : unsigned (7 downto 0);

begin

U1: process (Clk,Rst)
begin
  if Rst='1' then
    Cnt <= (others=>'0');
  elsif rising_edge(Clk) then
    Cnt <= Cnt + 1;
  end if;
end process U1;

U2: PWMout <= '1' when unsigned(Din(7 downto 0)) >= Cnt or Din(8)='1'
         else '0';

end RTL_Comparator;



-- -----------------------------------------
    Architecture RTL_Comp of PWM is
-- -----------------------------------------
-- Simple PWM, counter + comparator solution + output register.
-- Minimal the number of switchings.

signal Cnt : unsigned (7 downto 0);

begin

process (Clk,Rst)
begin
  if Rst='1' then
    Cnt <= (others=>'0');
    PWMout <= '0';
  elsif rising_edge(Clk) then
    Cnt <= Cnt + 1;
    if unsigned(Din(7 downto 0)) >= Cnt or Din(8)='1' then
      PWMout <= '1';
    else
      PWMout <= '0';
    end if;
  end if;
end process;

end RTL_Comp;