buzz1.v

数字电子琴控制器的ＶＥＲＩＬＯＧ代码

//简易电子琴
module buzz1 ( SW,CLK,BUZZ,LED);
	input CLK;
	input [3:0] SW;
	output BUZZ;
	output [7:0] LED;
	
	reg buzzout_reg;
	reg [31:0] counter,counter_end;
	reg [7:0] keyin_reg;

	always @ (posedge CLK)
	begin
		counter=counter+1;
		if((counter==counter_end)&(!(counter_end==32'h000ffff0)))
			begin
			counter=32'h00000000;
			buzzout_reg=~buzzout_reg;
			end
	end

	always @ (SW)
	begin
		keyin_reg={4'b1111,SW};
		case(keyin_reg)
		8'b11111110:counter_end=32'h00017572;   //中音1    
		8'b11111101:counter_end=32'h00014cba;	//中音2   
		8'b11111011:counter_end=32'h00012860;	//中音3   
		8'b11110111:counter_end=32'h0001176a;	//
		8'b11101111:counter_end=32'h00001b8d;	//
		8'b11011111:counter_end=32'h0000188b;	//
		8'b10111111:counter_end=32'h000015dd;	//
		8'b01111111:counter_end=32'h000014a3;	//高音1   
		8'b11111100:counter_end=32'h00001263;	//
		8'b11111010:counter_end=32'h00001061;	//
		8'b11110110:counter_end=32'h00000f76;	//
		8'b11101110:counter_end=32'h00000dc6;	//高音5   
		8'b11011110:counter_end=32'h00000c45;
		8'b10111110:counter_end=32'h00000ae8;
		default:counter_end=32'h000ffff0;
		endcase
	end

	assign BUZZ=buzzout_reg;
	assign LED=keyin_reg;
endmodule