fosc.v

频率计

module fosc (J,CLK,SEG,SL);
input [20:0]J;
input CLK;
output [7:0] SEG;
output [3:0] SL;

wire clkx;

reg [31:0] count;
reg [15:0] min,min1;
reg [7:0] lddat_reg;
reg [3:0] ldsel_reg,ledbuf;
reg sec,flag;

assign clkx=J[1];	// 输入信号，频率测试对象信号

always @ (negedge CLK)
	begin
	count=count+1;
	if(count==32'd25000000)
		begin
			sec=~sec;
			count=32'h00000000;
		end
	end

always @ (count[11:10])
	begin
		case(count[11:10])
			2'b00:ledbuf=min[3:0];
			2'b01:ledbuf=min[7:4];
			2'b10:ledbuf=min[11:8];
			2'b11:ledbuf=min[15:12];
		endcase
	end

always	@ (ledbuf)
	begin
		case(ledbuf)
			4'h0: lddat_reg = 8'hc0;
			4'h1: lddat_reg = 8'hf9;				//显示1
			4'h2: lddat_reg = 8'ha4;				//显示2
			4'h3: lddat_reg = 8'hb0;				//显示3
			4'h4: lddat_reg = 8'h99;				//显示4
			4'h5: lddat_reg = 8'h92;				//显示5
			4'h6: lddat_reg = 8'h82;				//显示6
			4'h7: lddat_reg = 8'hf8;				//显示7
			4'h8: lddat_reg = 8'h80;				//显示8
			4'h9: lddat_reg = 8'h90;				//显示9      
			4'ha: lddat_reg = 8'h88;				//显示a   
			4'hb: lddat_reg = 8'h83;				//显示b
			4'hc: lddat_reg = 8'hc6;				//显示c
			4'hd: lddat_reg = 8'ha1;				//显示d
			4'he: lddat_reg = 8'h86;				//显示e
			4'hf: lddat_reg = 8'h8e;				//显示f
		endcase
	end

always @ (count[11:10])
	begin
		case(count[11:10])
			2'b00:ldsel_reg=4'b0111;
			2'b01:ldsel_reg=4'b1011;
			2'b10:ldsel_reg=4'b1101;
			2'b11:ldsel_reg=4'b1110;
		endcase
	end

always @ (posedge clkx)
	begin
		if(sec)
		begin
		flag=1;
		min1[3:0]=min1[3:0]+1;
			if(min1[3:0]>4'h9)
				begin
					min1[3:0]=4'h0;
					min1[7:4]=min1[7:4]+1;
					if(min1[7:4]>4'h9)
						begin
							min1[7:4]=4'h0;
							min1[11:8]=min1[11:8]+1;
							if(min1[11:8]>4'h9)
								begin
									min1[11:8]=4'h0;
									min1[15:12]=min1[15:12]+1;
									if(min1[15:12]>4'h9) min1[15:12]=4'h0;
								end
						end
				end
		end
		else if(flag)
			begin
				flag=0;
				min[15:0]=min1[15:0];
				min1=16'h0;
			end		
	end

assign SEG=lddat_reg;
assign SL=ldsel_reg;	 

endmodule