📄 top.v
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`include "max.v"`include "lev.v"`include "rom_wave_out.v"`timescale 1ns/1ns`define data_width 4module top(level,max_num, addr_counter,data,clk,rst,en); output [`data_width-1:0] level; wire [`data_width-1:0] level; output [`data_width-1:0] max_num; wire [`data_width-1:0] max_num; output [`data_width-1:0] data; wire [`data_width-1:0] data; input clk; wire clk; input rst; input en; output [`data_width-1:0] addr_counter; reg [`data_width:0] addr_counter; reg max_ena,out_max_en,read_en,lev_ena; reg[3:0] state; parameter idle=2'b00, get_data=2'b01, cal_max=2'b10, get_lev=2'b11; always @ (posedge clk or negedge rst) if(!rst) begin max_ena<=1'b0; out_max_en<=1'b0; read_en<=1'b0; lev_ena<=1'b0; state<=idle; addr_counter<=5'b0_0000; end else if (en) begin case(state) idle: //if (en) begin state<=get_data; read_en<=1'b1; addr_counter<=5'b0_0000; end // else state<=idle; get_data: begin read_en<=1'b0; max_ena<=1'b1; addr_counter<=addr_counter+1'b1; state<=cal_max; end cal_max: if (addr_counter==5'b1_0001) begin max_ena<=1'b0; lev_ena<=1'b1; out_max_en<=1'b1; state<=get_lev; end else begin read_en<=1'b1; max_ena<=1'b0; state<=get_data; end get_lev: begin out_max_en<=1'b0; lev_ena<=1'b0; state<=idle; end default: state<=idle; endcase end max maxi(.max_num(max_num),.clk(clk),.rst(rst),.max_ena(max_ena),.out_max_en(out_max_en),.data_in(data)); rom_wave_out rom_wave_outi(.clk(clk),.read(read_en),.rst(rst),.addr( addr_counter),.data(data)); lev levi(.level(level),.lev_ena(lev_ena),.clk(clk),.rst(rst),.max_number(max_num));endmodule
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