📄 lev.v
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`timescale 1ns/1ns`define DATA_WIDTH 4 module lev(level,lev_ena,clk,rst,max_number); output [`DATA_WIDTH-1:0] level; reg [`DATA_WIDTH-1:0] level; input lev_ena; wire lev_ena; input clk; wire clk; input rst; wire rst; input [`DATA_WIDTH-1:0] max_number; wire [`DATA_WIDTH-1:0] max_number; always @(posedge clk or negedge rst) if(!rst) level <= 'b0; else if(lev_ena) begin if((max_number & 4'b1000) == 4'b1000) level <= 4'b0100; else if((max_number & 4'b0100) == 4'b0100) level <= 4'b0011; else if((max_number & 4'b0010) == 4'b0010) level <= 4'b0010; else if((max_number & 4'b0001) == 4'b0001) level <= 4'b0001; else level <= 4'b0000; end else level <= level; endmodule
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