rom_wave_out.v

来自「在quaters下写的比较数的大小输出」· Verilog 代码 · 共 39 行

 `define ADDR_DEPTH  4
 `define DATA_WIDTH  4

module rom_wave_out(clk,rst,read,addr,data);
  input                      clk;           
  wire                       clk;
  
  input                      rst;           
  wire                       rst;
  
  input                      read;           //Read enable signal of ROM
  wire                       read;
  
  input  [`ADDR_DEPTH-1:0]   addr;           //Address signal of ROM
  wire   [`ADDR_DEPTH-1:0]   addr;
  
  output [`DATA_WIDTH-1:0]   data;           //Data Signal of ROM
  wire   [`DATA_WIDTH-1:0]   data;
  
  reg    [`DATA_WIDTH-1:0]   mem_wave  [0:(1<<`ADDR_DEPTH)-1];//WAVE_OUT ROM 4*32(0~31)
  reg    [`DATA_WIDTH-1:0]   data_temp;
  

   
    initial
     begin   
        $readmemb("data_hex4x4.txt",mem_wave);
     end
         
  always @(posedge clk or negedge rst)
    if (!rst)
       data_temp <= 4'b0000;
    else if(read) data_temp <= mem_wave[addr];
      else data_temp <=data_temp;
      
  assign  data = data_temp;
  
endmodule