max.v

来自「在quaters下写的比较数的大小输出」· Verilog 代码 · 共 41 行

`timescale 1ns/1ns
`define 	DATA_WIDTH 	4  
   
module max(max_num,clk,rst,max_ena,out_max_en,data_in);
  
  output [`DATA_WIDTH-1:0] max_num;
   wire [`DATA_WIDTH-1:0] max_num;
    
  input				 max_ena;
  wire				 max_ena;  
  
  input   out_max_en;
  wire   out_max_en;
  
  input 			clk;
  wire				clk;
  
  input		    rst;
  wire				 rst;  
  
  input     [`DATA_WIDTH-1:0]		data_in;
  wire     [`DATA_WIDTH-1:0]		data_in;
 
  reg      [7:0]                max_number;

  always @(posedge clk or negedge rst)
       if(!rst)
          max_number <= 0;
        else if(max_ena)
           begin
              if(data_in>max_number)
                 max_number <= data_in;
              else
                 max_number <= max_number; 
           end
        else   max_number <= max_number;       

    assign   max_num= out_max_en?max_number:4'b0;   
    //assign   max_num= max_number;        
   endmodule