_primary.vhd

来自「在quaters下写的比较数的大小输出」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity rom_wave_out is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        read            : in     vl_logic;
        addr            : in     vl_logic_vector(3 downto 0);
        data            : out    vl_logic_vector(3 downto 0)
    );
end rom_wave_out;