_primary.vhd

来自「在quaters下写的比较数的大小输出」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity top is
    generic(
        idle            : integer := 0;
        get_data        : integer := 1;
        cal_max         : integer := 2;
        get_lev         : integer := 3
    );
    port(
        level           : out    vl_logic_vector(3 downto 0);
        max_num         : out    vl_logic_vector(3 downto 0);
        addr_counter    : out    vl_logic_vector(4 downto 0);
        data            : out    vl_logic_vector(3 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        en              : in     vl_logic
    );
end top;