all_01.map.qmsg

eda 开发数字钟的设计具体编程代码和开发流程与设计图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 05 09:01:46 2007 " "Info: Processing started: Sun Aug 05 09:01:46 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off all_01 -c all_01 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off all_01 -c all_01" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "all_01.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file all_01.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 all_01 " "Info: Found entity 1: all_01" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HEX2DEC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file HEX2DEC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HEX2DEC-arc " "Info: Found design unit 1: HEX2DEC-arc" {  } { { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 HEX2DEC " "Info: Found entity 1: HEX2DEC" {  } { { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLOCK40.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLOCK40.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock40-arc " "Info: Found design unit 1: clock40-arc" {  } { { "CLOCK40.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock40 " "Info: Found entity 1: clock40" {  } { { "CLOCK40.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "all_01 " "Info: Elaborating entity \"all_01\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CLOCK_SPK.vhd 2 1 " "Warning: Using design file CLOCK_SPK.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_spk-arc " "Info: Found design unit 1: clock_spk-arc" {  } { { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock_spk " "Info: Found entity 1: clock_spk" {  } { { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK_SPK CLOCK_SPK:17 " "Info: Elaborating entity \"CLOCK_SPK\" for hierarchy \"CLOCK_SPK:17\"" {  } { { "all_01.bdf" "17" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 576 792 976 640 "17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock40 clock40:inst3 " "Info: Elaborating entity \"clock40\" for hierarchy \"clock40:inst3\"" {  } { { "all_01.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 568 560 656 664 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CYC_PLL.tdf 1 1 " "Warning: Using design file CYC_PLL.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CYC_PLL " "Info: Found entity 1: CYC_PLL" {  } { { "CYC_PLL.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CYC_PLL.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CYC_PLL CYC_PLL:inst " "Info: Elaborating entity \"CYC_PLL\" for hierarchy \"CYC_PLL:inst\"" {  } { { "all_01.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { -136 472 744 40 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll CYC_PLL:inst\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"CYC_PLL:inst\|altpll:altpll_component\"" {  } { { "CYC_PLL.tdf" "altpll_component" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CYC_PLL.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CYC_PLL:inst\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"CYC_PLL:inst\|altpll:altpll_component\"" {  } { { "CYC_PLL.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CYC_PLL.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CLOCK2.vhd 2 1 " "Warning: Using design file CLOCK2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock2-arc " "Info: Found design unit 1: clock2-arc" {  } { { "CLOCK2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock2 " "Info: Found entity 1: clock2" {  } { { "CLOCK2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2.vhd" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK2 CLOCK2:inst2 " "Info: Elaborating entity \"CLOCK2\" for hierarchy \"CLOCK2:inst2\"" {  } { { "all_01.bdf" "inst2" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 104 1296 1432 152 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CLOCK2500.vhd 2 1 " "Warning: Using design file CLOCK2500.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock2500-arc " "Info: Found design unit 1: clock2500-arc" {  } { { "CLOCK2500.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2500.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock2500 " "Info: Found entity 1: clock2500" {  } { { "CLOCK2500.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2500.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}