fff.vhd

来自「eda 开发数字钟的设计具体编程代码和开发流程与设计图」· VHDL 代码 · 共 67 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fff is
  port(clkin:in std_logic;
       set_hh:in std_logic;

       set_mm:in std_logic; 
       set_ss:in std_logic;
       hh   :in integer range 0 to 255;  
       mm   :in integer range 0 to 255;  
       ss   :in integer range 0 to 255;  
       o_hh  :out integer range 0 to 255;  
       o_mm  :out integer range 0 to 255;  
       o_ss  :out integer range 0 to 255  
       );
end entity;

architecture arc of fff is
      signal abc:std_logic_vector(3 downto 1);
       begin
       abc <= (set_hh)&(set_mm)&(set_ss);
    process(abc)
  variable var_hh:integer range 0 to 255;
  variable var_mm:integer range 0 to 255;
  variable var_ss:integer range 0 to 255;
          
         begin
     if (clkin'event and clkin='1') then     
             
       case abc is
         when "011"=>
         var_hh:=hh;
         var_hh:=var_hh+1;
        
      
         when "101"=>
       var_mm:=mm;
       var_mm:=var_mm+1;
         
       when "110"=>
       var_ss:=ss;
         var_ss:=var_ss+1;
         
       
      when others=>
        
       var_hh := hh;
    	var_mm := mm;
    	var_ss := ss;
       end case;   

       
    end if;
       o_hh <= var_hh;
    	o_mm <= var_mm;
    	o_ss <= var_ss;
   end process;

      
      
    			 
               
end arc;