clock4.vhd

来自「eda 开发数字钟的设计具体编程代码和开发流程与设计图」· VHDL 代码 · 共 32 行

--*************************************************************************************--
--Colour Sort Machine/Four dividing clock module V1.0/01.11.30
--EIST Department,Nankai University
--Function part/clockall/4-dividing clock
--Src file:clock4.vhd
--Serial number:003
--2001----2002
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock4 is
  port(clk:in std_logic;
       clkout:out std_logic
       );
end clock4;

architecture arc of clock4 is
begin
  process(clk)
  variable count:std_logic_vector(1 downto 0);
  begin
    if (clk'event and clk='1') then
       count:=count+1;
    end if;
    clkout<=count(1);  
  end process;
end arc;