hex2dec.vhd

来自「eda 开发数字钟的设计具体编程代码和开发流程与设计图」· VHDL 代码 · 共 37 行

--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- FOR DISPLAY
entity HEX2DEC is
  port( HEX : in integer range 0 to 255; --0--59; 0x00--0x3B
		DEC : out integer range 0 to 255 --0--89;  0X00--0X59
       );
end entity;

architecture arc of HEX2DEC is
begin
	process(HEX) 
  	variable var_hh:integer range 0 to 255;
  	begin
		if (HEX <10 ) then
			DEC <= HEX;
		elsif (HEX < 20 ) then
			DEC <= HEX + 6;
		elsif (HEX < 30 ) then
			DEC <= HEX + 12;
		elsif (HEX < 40 ) then
			DEC <= HEX + 18;
		elsif (HEX < 50 ) then
			DEC <= HEX + 24;
		elsif (HEX < 60 ) then
			DEC <= HEX + 30;
		else
			DEC <= 255;
		end if;   
  	end process;
end arc;