adc0809.tan.qmsg

adc0809的fpga时序电路接口程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st6 " "Info: Detected ripple clock \"current_state.st6\" as buffer" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "current_state.st6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register current_state.st5 current_state.st6 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"current_state.st5\" and destination register \"current_state.st6\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.682 ns + Longest register register " "Info: + Longest register to register delay is 0.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st5 1 REG LCFF_X27_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y7_N5; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { current_state.st5 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.366 ns) 0.682 ns current_state.st6 2 REG LCFF_X27_Y7_N17 3 " "Info: 2: + IC(0.316 ns) + CELL(0.366 ns) = 0.682 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.682 ns" { current_state.st5 current_state.st6 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 53.67 % ) " "Info: Total cell delay = 0.366 ns ( 53.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.316 ns ( 46.33 % ) " "Info: Total interconnect delay = 0.316 ns ( 46.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.682 ns" { current_state.st5 current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.682 ns" { current_state.st5 current_state.st6 } { 0.000ns 0.316ns } { 0.000ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.350 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.537 ns) 2.350 ns current_state.st6 3 REG LCFF_X27_Y7_N17 3 " "Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.239 ns" { clk~clkctrl current_state.st6 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.94 % ) " "Info: Total cell delay = 1.526 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.824 ns ( 35.06 % ) " "Info: Total interconnect delay = 0.824 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st6 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.350 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.537 ns) 2.350 ns current_state.st5 3 REG LCFF_X27_Y7_N5 2 " "Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N5; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.239 ns" { clk~clkctrl current_state.st5 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.94 % ) " "Info: Total cell delay = 1.526 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.824 ns ( 35.06 % ) " "Info: Total interconnect delay = 0.824 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st5 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st5 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st6 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st5 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st5 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.682 ns" { current_state.st5 current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.682 ns" { current_state.st5 current_state.st6 } { 0.000ns 0.316ns } { 0.000ns 0.366ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st6 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st5 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st5 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { current_state.st6 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { current_state.st6 } {  } {  } } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st3 eoc clk 4.081 ns register " "Info: tsu for register \"current_state.st3\" (data pin = \"eoc\", clock pin = \"clk\") is 4.081 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.467 ns + Longest pin register " "Info: + Longest pin to register delay is 6.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns eoc 1 PIN PIN_73 3 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_73; Fanout = 3; PIN Node = 'eoc'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.102 ns) + CELL(0.419 ns) 6.383 ns Selector0~4 2 COMB LCCOMB_X27_Y7_N26 1 " "Info: 2: + IC(5.102 ns) + CELL(0.419 ns) = 6.383 ns; Loc. = LCCOMB_X27_Y7_N26; Fanout = 1; COMB Node = 'Selector0~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.521 ns" { eoc Selector0~4 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.467 ns current_state.st3 3 REG LCFF_X27_Y7_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.467 ns; Loc. = LCFF_X27_Y7_N27; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector0~4 current_state.st3 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.365 ns ( 21.11 % ) " "Info: Total cell delay = 1.365 ns ( 21.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.102 ns ( 78.89 % ) " "Info: Total interconnect delay = 5.102 ns ( 78.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.467 ns" { eoc Selector0~4 current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.467 ns" { eoc eoc~combout Selector0~4 current_state.st3 } { 0.000ns 0.000ns 5.102ns 0.000ns } { 0.000ns 0.862ns 0.419ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.350 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.537 ns) 2.350 ns current_state.st3 3 REG LCFF_X27_Y7_N27 2 " "Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N27; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.239 ns" { clk~clkctrl current_state.st3 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.94 % ) " "Info: Total cell delay = 1.526 ns ( 64.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.824 ns ( 35.06 % ) " "Info: Total interconnect delay = 0.824 ns ( 35.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st3 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.467 ns" { eoc Selector0~4 current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.467 ns" { eoc eoc~combout Selector0~4 current_state.st3 } { 0.000ns 0.000ns 5.102ns 0.000ns } { 0.000ns 0.862ns 0.419ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.350 ns" { clk clk~clkctrl current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.350 ns" { clk clk~combout clk~clkctrl current_state.st3 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] regl\[0\] 8.656 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through register \"regl\[0\]\" is 8.656 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.389 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns current_state.st6 3 REG LCFF_X27_Y7_N17 3 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl current_state.st6 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.631 ns) + CELL(0.000 ns) 3.231 ns current_state.st6~clkctrl 4 COMB CLKCTRL_G4 8 " "Info: 4: + IC(0.631 ns) + CELL(0.000 ns) = 3.231 ns; Loc. = CLKCTRL_G4; Fanout = 8; COMB Node = 'current_state.st6~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.631 ns" { current_state.st6 current_state.st6~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.008 ns) + CELL(0.150 ns) 4.389 ns regl\[0\] 5 REG LCCOMB_X10_Y6_N16 1 " "Info: 5: + IC(1.008 ns) + CELL(0.150 ns) = 4.389 ns; Loc. = LCCOMB_X10_Y6_N16; Fanout = 1; REG Node = 'regl\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.158 ns" { current_state.st6~clkctrl regl[0] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.926 ns ( 43.88 % ) " "Info: Total cell delay = 1.926 ns ( 43.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.463 ns ( 56.12 % ) " "Info: Total interconnect delay = 2.463 ns ( 56.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.389 ns" { clk clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.389 ns" { clk clk~combout clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[0] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.631ns 1.008ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.267 ns + Longest register pin " "Info: + Longest register to pin delay is 4.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns regl\[0\] 1 REG LCCOMB_X10_Y6_N16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X10_Y6_N16; Fanout = 1; REG Node = 'regl\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { regl[0] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(2.642 ns) 4.267 ns q\[0\] 2 PIN PIN_80 0 " "Info: 2: + IC(1.625 ns) + CELL(2.642 ns) = 4.267 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.267 ns" { regl[0] q[0] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 61.92 % ) " "Info: Total cell delay = 2.642 ns ( 61.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.625 ns ( 38.08 % ) " "Info: Total interconnect delay = 1.625 ns ( 38.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.267 ns" { regl[0] q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.267 ns" { regl[0] q[0] } { 0.000ns 1.625ns } { 0.000ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.389 ns" { clk clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.389 ns" { clk clk~combout clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[0] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.631ns 1.008ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.150ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.267 ns" { regl[0] q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.267 ns" { regl[0] q[0] } { 0.000ns 1.625ns } { 0.000ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "abc_in\[2\] abc_out\[2\] 8.927 ns Longest " "Info: Longest tpd from source pin \"abc_in\[2\]\" to destination pin \"abc_out\[2\]\" is 8.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns abc_in\[2\] 1 PIN PIN_52 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'abc_in\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { abc_in[2] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.279 ns) + CELL(2.798 ns) 8.927 ns abc_out\[2\] 2 PIN PIN_48 0 " "Info: 2: + IC(5.279 ns) + CELL(2.798 ns) = 8.927 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'abc_out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.077 ns" { abc_in[2] abc_out[2] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.648 ns ( 40.86 % ) " "Info: Total cell delay = 3.648 ns ( 40.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.279 ns ( 59.14 % ) " "Info: Total interconnect delay = 5.279 ns ( 59.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.927 ns" { abc_in[2] abc_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.927 ns" { abc_in[2] abc_in[2]~combout abc_out[2] } { 0.000ns 0.000ns 5.279ns } { 0.000ns 0.850ns 2.798ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}