adc0809.tan.qmsg

adc0809的fpga时序电路接口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 26 09:29:44 2007 " "Info: Processing started: Tue Jun 26 09:29:44 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ADC0809 -c ADC0809 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC0809 -c ADC0809 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[0\] " "Warning: Node \"regl\[0\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[1\] " "Warning: Node \"regl\[1\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[2\] " "Warning: Node \"regl\[2\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[3\] " "Warning: Node \"regl\[3\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[4\] " "Warning: Node \"regl\[4\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[5\] " "Warning: Node \"regl\[5\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[6\] " "Warning: Node \"regl\[6\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[7\] " "Warning: Node \"regl\[7\]\" is a latch" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}