adc0809.tan.rpt

adc0809的fpga时序电路接口程序

; N/A   ; None         ; 7.635 ns   ; regl[3]           ; q[3]  ; clk        ;
; N/A   ; None         ; 6.773 ns   ; current_state.st5 ; en    ; clk        ;
; N/A   ; None         ; 6.458 ns   ; current_state.st6 ; en    ; clk        ;
; N/A   ; None         ; 6.057 ns   ; current_state.st2 ; start ; clk        ;
; N/A   ; None         ; 6.009 ns   ; current_state.st1 ; ale   ; clk        ;
+-------+--------------+------------+-------------------+-------+------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 8.927 ns        ; abc_in[2] ; abc_out[2] ;
; N/A   ; None              ; 8.870 ns        ; abc_in[0] ; abc_out[0] ;
; N/A   ; None              ; 8.276 ns        ; abc_in[1] ; abc_out[1] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 2.185 ns  ; d[1] ; regl[1]           ; clk      ;
; N/A           ; None        ; 2.081 ns  ; d[0] ; regl[0]           ; clk      ;
; N/A           ; None        ; 1.998 ns  ; d[2] ; regl[2]           ; clk      ;
; N/A           ; None        ; -1.229 ns ; d[3] ; regl[3]           ; clk      ;
; N/A           ; None        ; -1.494 ns ; d[4] ; regl[4]           ; clk      ;
; N/A           ; None        ; -1.555 ns ; d[5] ; regl[5]           ; clk      ;
; N/A           ; None        ; -1.693 ns ; d[7] ; regl[7]           ; clk      ;
; N/A           ; None        ; -1.701 ns ; d[6] ; regl[6]           ; clk      ;
; N/A           ; None        ; -3.705 ns ; eoc  ; current_state.st5 ; clk      ;
; N/A           ; None        ; -3.810 ns ; eoc  ; current_state.st4 ; clk      ;
; N/A           ; None        ; -3.851 ns ; eoc  ; current_state.st3 ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 26 09:29:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC0809 -c ADC0809 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "regl[0]" is a latch
    Warning: Node "regl[1]" is a latch
    Warning: Node "regl[2]" is a latch
    Warning: Node "regl[3]" is a latch
    Warning: Node "regl[4]" is a latch
    Warning: Node "regl[5]" is a latch
    Warning: Node "regl[6]" is a latch
    Warning: Node "regl[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.st6" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "current_state.st5" and destination register "current_state.st6"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.682 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y7_N5; Fanout = 2; REG Node = 'current_state.st5'
            Info: 2: + IC(0.316 ns) + CELL(0.366 ns) = 0.682 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'
            Info: Total cell delay = 0.366 ns ( 53.67 % )
            Info: Total interconnect delay = 0.316 ns ( 46.33 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.350 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'
                Info: Total cell delay = 1.526 ns ( 64.94 % )
                Info: Total interconnect delay = 0.824 ns ( 35.06 % )
            Info: - Longest clock path from clock "clk" to source register is 2.350 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N5; Fanout = 2; REG Node = 'current_state.st5'
                Info: Total cell delay = 1.526 ns ( 64.94 % )
                Info: Total interconnect delay = 0.824 ns ( 35.06 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "current_state.st3" (data pin = "eoc", clock pin = "clk") is 4.081 ns
    Info: + Longest pin to register delay is 6.467 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_73; Fanout = 3; PIN Node = 'eoc'
        Info: 2: + IC(5.102 ns) + CELL(0.419 ns) = 6.383 ns; Loc. = LCCOMB_X27_Y7_N26; Fanout = 1; COMB Node = 'Selector0~4'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.467 ns; Loc. = LCFF_X27_Y7_N27; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 1.365 ns ( 21.11 % )
        Info: Total interconnect delay = 5.102 ns ( 78.89 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.350 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.350 ns; Loc. = LCFF_X27_Y7_N27; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 1.526 ns ( 64.94 % )
        Info: Total interconnect delay = 0.824 ns ( 35.06 % )
Info: tco from clock "clk" to destination pin "q[0]" through register "regl[0]" is 8.656 ns
    Info: + Longest clock path from clock "clk" to source register is 4.389 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'
        Info: 4: + IC(0.631 ns) + CELL(0.000 ns) = 3.231 ns; Loc. = CLKCTRL_G4; Fanout = 8; COMB Node = 'current_state.st6~clkctrl'
        Info: 5: + IC(1.008 ns) + CELL(0.150 ns) = 4.389 ns; Loc. = LCCOMB_X10_Y6_N16; Fanout = 1; REG Node = 'regl[0]'
        Info: Total cell delay = 1.926 ns ( 43.88 % )
        Info: Total interconnect delay = 2.463 ns ( 56.12 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.267 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X10_Y6_N16; Fanout = 1; REG Node = 'regl[0]'
        Info: 2: + IC(1.625 ns) + CELL(2.642 ns) = 4.267 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'q[0]'
        Info: Total cell delay = 2.642 ns ( 61.92 % )
        Info: Total interconnect delay = 1.625 ns ( 38.08 % )
Info: Longest tpd from source pin "abc_in[2]" to destination pin "abc_out[2]" is 8.927 ns
    Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'abc_in[2]'
    Info: 2: + IC(5.279 ns) + CELL(2.798 ns) = 8.927 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'abc_out[2]'
    Info: Total cell delay = 3.648 ns ( 40.86 % )
    Info: Total interconnect delay = 5.279 ns ( 59.14 % )
Info: th for register "regl[1]" (data pin = "d[1]", clock pin = "clk") is 2.185 ns
    Info: + Longest clock path from clock "clk" to destination register is 4.542 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'
        Info: 4: + IC(0.631 ns) + CELL(0.000 ns) = 3.231 ns; Loc. = CLKCTRL_G4; Fanout = 8; COMB Node = 'current_state.st6~clkctrl'
        Info: 5: + IC(1.036 ns) + CELL(0.275 ns) = 4.542 ns; Loc. = LCCOMB_X1_Y11_N0; Fanout = 1; REG Node = 'regl[1]'
        Info: Total cell delay = 2.051 ns ( 45.16 % )
        Info: Total interconnect delay = 2.491 ns ( 54.84 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 2.357 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'd[1]'
        Info: 2: + IC(0.930 ns) + CELL(0.438 ns) = 2.357 ns; Loc. = LCCOMB_X1_Y11_N0; Fanout = 1; REG Node = 'regl[1]'
        Info: Total cell delay = 1.427 ns ( 60.54 % )
        Info: Total interconnect delay = 0.930 ns ( 39.46 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Processing ended: Tue Jun 26 09:29:44 2007
    Info: Elapsed time: 00:00:00